From: Vincent Whitchurch <vincent.whitchurch@axis.com> To: <krzysztof.kozlowski@linaro.org>, <tglx@linutronix.de>, <daniel.lezcano@linaro.org> Cc: <kernel@axis.com>, Vincent Whitchurch <vincent.whitchurch@axis.com>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-samsung-soc@vger.kernel.org>, <alim.akhtar@samsung.com>, <devicetree@vger.kernel.org>, <robh+dt@kernel.org> Subject: [PATCH v4 1/4] dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support Date: Thu, 9 Jun 2022 13:27:35 +0200 [thread overview] Message-ID: <20220609112738.359385-2-vincent.whitchurch@axis.com> (raw) In-Reply-To: <20220609112738.359385-1-vincent.whitchurch@axis.com> The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global free-running counter and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots (via the A53), it should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this hardware, add a compatible for the MCT as well as two new properties to describe the hardware-mandated sharing of the FRC and dedicating local timers to specific processors. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> --- Notes: v4: - Add Krzysztof's Reviewed-by. v3: - Add all required bindings for ARTPEC-8 in one patch - Rename and split local-timer-only to samsung,local-timers and samsung,frc-shared - Restrict above properties to the ARTPEC-8 compatible. - Rewrite descriptions of properties to hopefully describe hardware. v2: - Use devicetree property instead of module parameter. .../timer/samsung,exynos4210-mct.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 9c81d00b12e0..829bd2227f7c 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos4412-mct - items: - enum: + - axis,artpec8-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -45,6 +46,19 @@ properties: reg: maxItems: 1 + samsung,frc-shared: + type: boolean + description: | + Indicates that the hardware requires that this processor share the + free-running counter with a different (main) processor. + + samsung,local-timers: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 + description: | + List of indices of local timers usable from this processor. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer @@ -74,6 +88,17 @@ required: - reg allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - axis,artpec8-mct + then: + properties: + samsung,local-timers: false + samsung,frc-shared: false - if: properties: compatible: @@ -101,6 +126,7 @@ allOf: compatible: contains: enum: + - axis,artpec8-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Vincent Whitchurch <vincent.whitchurch@axis.com> To: <krzysztof.kozlowski@linaro.org>, <tglx@linutronix.de>, <daniel.lezcano@linaro.org> Cc: <kernel@axis.com>, Vincent Whitchurch <vincent.whitchurch@axis.com>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-samsung-soc@vger.kernel.org>, <alim.akhtar@samsung.com>, <devicetree@vger.kernel.org>, <robh+dt@kernel.org> Subject: [PATCH v4 1/4] dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support Date: Thu, 9 Jun 2022 13:27:35 +0200 [thread overview] Message-ID: <20220609112738.359385-2-vincent.whitchurch@axis.com> (raw) In-Reply-To: <20220609112738.359385-1-vincent.whitchurch@axis.com> The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global free-running counter and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots (via the A53), it should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this hardware, add a compatible for the MCT as well as two new properties to describe the hardware-mandated sharing of the FRC and dedicating local timers to specific processors. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> --- Notes: v4: - Add Krzysztof's Reviewed-by. v3: - Add all required bindings for ARTPEC-8 in one patch - Rename and split local-timer-only to samsung,local-timers and samsung,frc-shared - Restrict above properties to the ARTPEC-8 compatible. - Rewrite descriptions of properties to hopefully describe hardware. v2: - Use devicetree property instead of module parameter. .../timer/samsung,exynos4210-mct.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 9c81d00b12e0..829bd2227f7c 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos4412-mct - items: - enum: + - axis,artpec8-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -45,6 +46,19 @@ properties: reg: maxItems: 1 + samsung,frc-shared: + type: boolean + description: | + Indicates that the hardware requires that this processor share the + free-running counter with a different (main) processor. + + samsung,local-timers: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 + description: | + List of indices of local timers usable from this processor. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer @@ -74,6 +88,17 @@ required: - reg allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - axis,artpec8-mct + then: + properties: + samsung,local-timers: false + samsung,frc-shared: false - if: properties: compatible: @@ -101,6 +126,7 @@ allOf: compatible: contains: enum: + - axis,artpec8-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-06-09 11:28 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-09 11:27 [PATCH v4 0/4] clocksource: Add MCT support for ARTPEC-8 Vincent Whitchurch 2022-06-09 11:27 ` Vincent Whitchurch 2022-06-09 11:27 ` Vincent Whitchurch [this message] 2022-06-09 11:27 ` [PATCH v4 1/4] dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support Vincent Whitchurch 2022-10-04 9:27 ` [tip: timers/core] " tip-bot2 for Vincent Whitchurch 2022-06-09 11:27 ` [PATCH v4 2/4] clocksource/drivers/exynos_mct: Support frc-shared property Vincent Whitchurch 2022-06-09 11:27 ` Vincent Whitchurch 2022-10-04 9:27 ` [tip: timers/core] " tip-bot2 for Vincent Whitchurch 2022-06-09 11:27 ` [PATCH v4 3/4] clocksource/drivers/exynos_mct: Support local-timers property Vincent Whitchurch 2022-06-09 11:27 ` Vincent Whitchurch 2022-06-21 13:11 ` Krzysztof Kozlowski 2022-06-21 13:11 ` Krzysztof Kozlowski 2022-09-07 8:59 ` Vincent Whitchurch 2022-09-07 8:59 ` Vincent Whitchurch 2022-09-07 9:07 ` Daniel Lezcano 2022-09-07 9:07 ` Daniel Lezcano 2022-10-04 9:27 ` [tip: timers/core] " tip-bot2 for Vincent Whitchurch 2022-06-09 11:27 ` [PATCH v4 4/4] clocksource/drivers/exynos_mct: Enable building on ARTPEC Vincent Whitchurch 2022-06-09 11:27 ` Vincent Whitchurch 2022-10-04 9:27 ` [tip: timers/core] " tip-bot2 for Vincent Whitchurch 2022-09-07 9:08 ` [PATCH v4 0/4] clocksource: Add MCT support for ARTPEC-8 Daniel Lezcano 2022-09-07 9:08 ` Daniel Lezcano
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