From: Robert Beckett <bob.beckett@collabora.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: kernel@collabora.com,
"Robert Beckett" <bob.beckett@collabora.com>,
"Matthew Auld" <matthew.auld@intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH v6 03/10] drm/i915/ttm: only trust snooping for dgfx when deciding default cache_level
Date: Fri, 17 Jun 2022 19:05:09 +0000 [thread overview]
Message-ID: <20220617190516.2805572-4-bob.beckett@collabora.com> (raw)
In-Reply-To: <20220617190516.2805572-1-bob.beckett@collabora.com>
By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now and maintain previous behaviour.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 4c1de0b4a10f..40249fa28a7a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -46,7 +46,9 @@ static enum i915_cache_level
i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
struct ttm_tt *ttm)
{
- return ((HAS_LLC(i915) || HAS_SNOOP(i915)) &&
+ bool can_snoop = HAS_SNOOP(i915) && IS_DGFX(i915);
+
+ return ((HAS_LLC(i915) || can_snoop) &&
!i915_ttm_gtt_binds_lmem(res) &&
ttm->caching == ttm_cached) ? I915_CACHE_LLC :
I915_CACHE_NONE;
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Robert Beckett <bob.beckett@collabora.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: "Robert Beckett" <bob.beckett@collabora.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
kernel@collabora.com, "Matthew Auld" <matthew.auld@intel.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH v6 03/10] drm/i915/ttm: only trust snooping for dgfx when deciding default cache_level
Date: Fri, 17 Jun 2022 19:05:09 +0000 [thread overview]
Message-ID: <20220617190516.2805572-4-bob.beckett@collabora.com> (raw)
In-Reply-To: <20220617190516.2805572-1-bob.beckett@collabora.com>
By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now and maintain previous behaviour.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 4c1de0b4a10f..40249fa28a7a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -46,7 +46,9 @@ static enum i915_cache_level
i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
struct ttm_tt *ttm)
{
- return ((HAS_LLC(i915) || HAS_SNOOP(i915)) &&
+ bool can_snoop = HAS_SNOOP(i915) && IS_DGFX(i915);
+
+ return ((HAS_LLC(i915) || can_snoop) &&
!i915_ttm_gtt_binds_lmem(res) &&
ttm->caching == ttm_cached) ? I915_CACHE_LLC :
I915_CACHE_NONE;
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Robert Beckett <bob.beckett@collabora.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
kernel@collabora.com, "Matthew Auld" <matthew.auld@intel.com>,
linux-kernel@vger.kernel.org
Subject: [Intel-gfx] [PATCH v6 03/10] drm/i915/ttm: only trust snooping for dgfx when deciding default cache_level
Date: Fri, 17 Jun 2022 19:05:09 +0000 [thread overview]
Message-ID: <20220617190516.2805572-4-bob.beckett@collabora.com> (raw)
In-Reply-To: <20220617190516.2805572-1-bob.beckett@collabora.com>
By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now and maintain previous behaviour.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 4c1de0b4a10f..40249fa28a7a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -46,7 +46,9 @@ static enum i915_cache_level
i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
struct ttm_tt *ttm)
{
- return ((HAS_LLC(i915) || HAS_SNOOP(i915)) &&
+ bool can_snoop = HAS_SNOOP(i915) && IS_DGFX(i915);
+
+ return ((HAS_LLC(i915) || can_snoop) &&
!i915_ttm_gtt_binds_lmem(res) &&
ttm->caching == ttm_cached) ? I915_CACHE_LLC :
I915_CACHE_NONE;
--
2.25.1
next prev parent reply other threads:[~2022-06-17 19:05 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-17 19:05 [PATCH v6 00/10] drm/i915: ttm for stolen Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` [PATCH v6 01/10] drm/i915/ttm: dont trample cache_level overrides during ttm move Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 19:05 ` [PATCH v6 02/10] drm/i915: limit ttm to dma32 for i965G[M] Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 19:05 ` Robert Beckett [this message]
2022-06-17 19:05 ` [Intel-gfx] [PATCH v6 03/10] drm/i915/ttm: only trust snooping for dgfx when deciding default cache_level Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 19:05 ` [PATCH v6 04/10] drm/i915/gem: selftest should not attempt mmap of private regions Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 19:05 ` [PATCH v6 05/10] drm/i915: instantiate ttm ranger manager for stolen memory Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 19:05 ` [PATCH v6 06/10] drm/i915: sanitize mem_flags for stolen buffers Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 19:05 ` [PATCH v6 07/10] drm/i915: ttm move/clear logic fix Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 19:05 ` [PATCH v6 08/10] drm/i915: allow memory region creators to alloc and free the region Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 19:05 ` [PATCH v6 09/10] drm/i915/ttm: add buffer pin on alloc flag Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 19:05 ` [PATCH v6 10/10] drm/i915: stolen memory use ttm backend Robert Beckett
2022-06-17 19:05 ` [Intel-gfx] " Robert Beckett
2022-06-17 19:05 ` Robert Beckett
2022-06-17 20:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: ttm for stolen (rev2) Patchwork
2022-06-17 20:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-18 10:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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