[PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port

From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Cc: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<michals@xilinx.com>, <robh@kernel.org>,
	Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Subject: [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port
Date: Sat, 18 Jun 2022 08:14:57 +0530	[thread overview]
Message-ID: <20220618024459.7554-1-bharat.kumar.gogada@xilinx.com> (raw)

Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.

Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
  to enable and handle legacy interrupts.

Changes in v5:
- Added of_device_get_match_data to identify CPM version.

Bharat Kumar Gogada (2):
  dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port

 .../bindings/pci/xilinx-versal-cpm.yaml       | 48 ++++++++++++--
 drivers/pci/controller/pcie-xilinx-cpm.c      | 62 ++++++++++++++++++-
 2 files changed, 103 insertions(+), 7 deletions(-)

-- 
2.17.1