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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com
Subject: [Intel-gfx] [PATCH v3 5/9] drm/i915/dgfx: Add has_lmem_sr
Date: Fri, 24 Jun 2022 21:29:18 +0530	[thread overview]
Message-ID: <20220624155922.7435-6-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20220624155922.7435-1-anshuman.gupta@intel.com>

Add has_lmem_sr platform specific flag to know,
whether platform has VRAM self refresh support.
As of now both DG1 and DG2 client platforms supports VRAM self refresh
with D3Cold but let it enable first on DG2 as primary lead platform
for D3Cold support. Let it get enable on DG1 once this feature
is stable.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 1 +
 drivers/gpu/drm/i915/i915_pci.c          | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a68777948db9..80de5b2eaf53 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1301,6 +1301,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_LMEM_SR(i915) (INTEL_INFO(i915)->has_lmem_sr)
 
 /*
  * Platform has the dedicated compression control state for each lmem surfaces
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5e51fc29bb8b..04aad54033dd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -917,6 +917,7 @@ static const struct intel_device_info dg1_info = {
 	DGFX_FEATURES,
 	.graphics.rel = 10,
 	PLATFORM(INTEL_DG1),
+	.has_lmem_sr = 0,
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 	.require_force_probe = 1,
 	.platform_engine_mask =
@@ -1074,6 +1075,7 @@ static const struct intel_device_info xehpsdv_info = {
 static const struct intel_device_info dg2_info = {
 	DG2_FEATURES,
 	XE_LPD_FEATURES,
+	.has_lmem_sr = 1,
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 	.require_force_probe = 1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6c9564429509..0b2dde67b8f8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -155,6 +155,7 @@ enum intel_ppgtt_type {
 	func(has_l3_ccs_read); \
 	func(has_l3_dpf); \
 	func(has_llc); \
+	func(has_lmem_sr); \
 	func(has_logical_ring_contexts); \
 	func(has_logical_ring_elsq); \
 	func(has_media_ratio_mode); \
-- 
2.26.2


  parent reply	other threads:[~2022-06-24 16:00 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-24 15:59 [Intel-gfx] [PATCH v3 0/9] DG2 VRAM_SR Support Anshuman Gupta
2022-06-24 15:59 ` [Intel-gfx] [PATCH v3 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support Anshuman Gupta
2022-06-24 15:59 ` [Intel-gfx] [PATCH v3 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support Anshuman Gupta
2022-06-24 15:59 ` [Intel-gfx] [PATCH v3 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform Anshuman Gupta
2022-06-24 15:59 ` [Intel-gfx] [PATCH v3 4/9] drm/i915/dg2: DG2 MBD config Anshuman Gupta
2022-06-24 15:59 ` Anshuman Gupta [this message]
2022-06-24 15:59 ` [Intel-gfx] [PATCH v3 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD Anshuman Gupta
2022-06-24 15:59 ` [Intel-gfx] [PATCH v3 7/9] Drm/i915/rpm: Enable D3Cold VRAM SR Support Anshuman Gupta
2022-06-24 15:59 ` [Intel-gfx] [PATCH v3 8/9] drm/i915/xehpsdv: Store lmem region in gt Anshuman Gupta
2022-06-24 15:59 ` [Intel-gfx] [PATCH v3 9/9] drm/i915/rpm: d3cold Policy Anshuman Gupta
2022-06-24 16:28 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for DG2 VRAM_SR Support (rev4) Patchwork

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