From: Irui Wang <irui.wang@mediatek.com> To: Hans Verkuil <hverkuil-cisco@xs4all.nl>, Mauro Carvalho Chehab <mchehab@kernel.org>, Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Tzung-Bi Shih <tzungbi@chromium.org>, <angelogioacchino.delregno@collabora.com>, <nicolas.dufresne@collabora.com>, <wenst@chromium.org> Cc: <Project_Global_Chrome_Upstream_Group@mediatek.com>, <linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, Tomasz Figa <tfiga@chromium.org>, <xia.jiang@mediatek.com>, <maoguang.meng@mediatek.com>, kyrie wu <kyrie.wu@mediatek.com>, <srv_heupstream@mediatek.com> Subject: [V10,1/7] dt-bindings: mediatek: Add mediatek, mt8195-jpgenc compatible Date: Mon, 27 Jun 2022 10:56:19 +0800 [thread overview] Message-ID: <20220627025625.8956-2-irui.wang@mediatek.com> (raw) In-Reply-To: <20220627025625.8956-1-irui.wang@mediatek.com> From: kyrie wu <kyrie.wu@mediatek.com> Add mediatek,mt8195-jpgenc compatible to binding document. Signed-off-by: kyrie wu <kyrie.wu@mediatek.com> --- .../media/mediatek,mt8195-jpegenc.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml new file mode 100644 index 000000000000..7737d2ba8b8d --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek JPEG Encoder Device Tree Bindings + +maintainers: + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> + +description: |- + MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs + +properties: + compatible: + items: + - const: mediatek,mt8195-jpgenc + + mediatek,jpegenc-multi-core: + type: boolean + description: | + Indicates whether the jpeg encoder has multiple cores or not. + + power-domains: + maxItems: 1 + + iommus: + maxItems: 4 + description: | + Points to the respective IOMMU block with master port as argument, see + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + Ports are according to the HW. + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +# Required child node: +patternProperties: + "^jpgenc@[0-9a-f]+$": + type: object + description: | + The jpeg encoder hardware device node which should be added as subnodes to + the main jpeg node. + + properties: + compatible: + const: mediatek,mt8195-jpgenc-hw + + reg: + maxItems: 1 + + hw_id: + description: | + MT8195 encoding hardware id value. MT8195 has two encoding hardwares, + which is represented by this parameter. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: jpgenc + + power-domains: + maxItems: 1 + + required: + - compatible + - reg + - hw_id + - iommus + - interrupts + - clocks + - clock-names + - power-domains + + additionalProperties: false + +required: + - compatible + - power-domains + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/power/mt8195-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + jpgenc_master { + compatible = "mediatek,mt8195-jpgenc"; + mediatek,jpegenc-multi-core; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + jpgenc@1a030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1a030000 0 0x10000>; + hw_id = <0>; + iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + + jpgenc@1b030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1b030000 0 0x10000>; + hw_id = <1>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + }; -- 2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Irui Wang <irui.wang@mediatek.com> To: Hans Verkuil <hverkuil-cisco@xs4all.nl>, Mauro Carvalho Chehab <mchehab@kernel.org>, Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Tzung-Bi Shih <tzungbi@chromium.org>, <angelogioacchino.delregno@collabora.com>, <nicolas.dufresne@collabora.com>, <wenst@chromium.org> Cc: <Project_Global_Chrome_Upstream_Group@mediatek.com>, <linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, Tomasz Figa <tfiga@chromium.org>, <xia.jiang@mediatek.com>, <maoguang.meng@mediatek.com>, kyrie wu <kyrie.wu@mediatek.com>, <srv_heupstream@mediatek.com> Subject: [V10,1/7] dt-bindings: mediatek: Add mediatek, mt8195-jpgenc compatible Date: Mon, 27 Jun 2022 10:56:19 +0800 [thread overview] Message-ID: <20220627025625.8956-2-irui.wang@mediatek.com> (raw) In-Reply-To: <20220627025625.8956-1-irui.wang@mediatek.com> From: kyrie wu <kyrie.wu@mediatek.com> Add mediatek,mt8195-jpgenc compatible to binding document. Signed-off-by: kyrie wu <kyrie.wu@mediatek.com> --- .../media/mediatek,mt8195-jpegenc.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml new file mode 100644 index 000000000000..7737d2ba8b8d --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek JPEG Encoder Device Tree Bindings + +maintainers: + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> + +description: |- + MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs + +properties: + compatible: + items: + - const: mediatek,mt8195-jpgenc + + mediatek,jpegenc-multi-core: + type: boolean + description: | + Indicates whether the jpeg encoder has multiple cores or not. + + power-domains: + maxItems: 1 + + iommus: + maxItems: 4 + description: | + Points to the respective IOMMU block with master port as argument, see + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + Ports are according to the HW. + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +# Required child node: +patternProperties: + "^jpgenc@[0-9a-f]+$": + type: object + description: | + The jpeg encoder hardware device node which should be added as subnodes to + the main jpeg node. + + properties: + compatible: + const: mediatek,mt8195-jpgenc-hw + + reg: + maxItems: 1 + + hw_id: + description: | + MT8195 encoding hardware id value. MT8195 has two encoding hardwares, + which is represented by this parameter. + + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: jpgenc + + power-domains: + maxItems: 1 + + required: + - compatible + - reg + - hw_id + - iommus + - interrupts + - clocks + - clock-names + - power-domains + + additionalProperties: false + +required: + - compatible + - power-domains + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/power/mt8195-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + jpgenc_master { + compatible = "mediatek,mt8195-jpgenc"; + mediatek,jpegenc-multi-core; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + jpgenc@1a030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1a030000 0 0x10000>; + hw_id = <0>; + iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + + jpgenc@1b030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1b030000 0 0x10000>; + hw_id = <1>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + }; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-06-27 2:56 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-27 2:56 [V10,0/7] Enable two hardware jpeg encoder for MT8195 Irui Wang 2022-06-27 2:56 ` Irui Wang 2022-06-27 2:56 ` Irui Wang [this message] 2022-06-27 2:56 ` [V10,1/7] dt-bindings: mediatek: Add mediatek, mt8195-jpgenc compatible Irui Wang 2022-07-01 15:31 ` Rob Herring 2022-07-01 15:31 ` Rob Herring 2022-06-27 2:56 ` [V10,2/7] mtk-jpegenc: export jpeg encoder functions Irui Wang 2022-06-27 2:56 ` Irui Wang 2022-06-27 2:56 ` [V10,3/7] mtk-jpegenc: manage jpegenc multi-hardware Irui Wang 2022-06-27 2:56 ` Irui Wang 2022-06-27 2:56 ` [V10,4/7] mtk-jpegenc: add jpegenc timeout func interface Irui Wang 2022-06-27 2:56 ` Irui Wang 2022-06-27 2:56 ` [V10,5/7] mtk-jpegenc: add jpeg encode worker interface Irui Wang 2022-06-27 2:56 ` Irui Wang 2022-07-05 13:27 ` AngeloGioacchino Del Regno 2022-07-05 13:27 ` AngeloGioacchino Del Regno 2022-07-14 8:51 ` kyrie.wu 2022-07-14 8:51 ` kyrie.wu 2022-07-14 11:57 ` AngeloGioacchino Del Regno 2022-07-14 11:57 ` AngeloGioacchino Del Regno 2022-06-27 2:56 ` [V10,6/7] mtk-jpegenc: add output pic reorder interface Irui Wang 2022-06-27 2:56 ` Irui Wang 2022-06-27 2:56 ` [V10,7/7] mtk-jpegenc: add stop cmd interface for jpgenc Irui Wang 2022-06-27 2:56 ` Irui Wang 2022-07-05 12:56 ` [V10,0/7] Enable two hardware jpeg encoder for MT8195 AngeloGioacchino Del Regno 2022-07-05 12:56 ` AngeloGioacchino Del Regno 2022-07-05 13:38 ` AngeloGioacchino Del Regno 2022-07-05 13:38 ` AngeloGioacchino Del Regno 2022-07-14 8:46 ` kyrie.wu 2022-07-14 8:46 ` kyrie.wu
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