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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Joey Gouly <joey.gouly@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v6 19/27] arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation
Date: Wed, 29 Jun 2022 11:28:26 +0100	[thread overview]
Message-ID: <20220629102834.36569-20-broonie@kernel.org> (raw)
In-Reply-To: <20220629102834.36569-1-broonie@kernel.org>

Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions
in DDI0487H.a. No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 34 --------------
 arch/arm64/tools/sysreg         | 83 +++++++++++++++++++++++++++++++++
 2 files changed, 83 insertions(+), 34 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index a7ebfa17893a..089e2da3a5a9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -201,7 +201,6 @@
 #define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)
 #define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
 
-#define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
 #define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
 
 #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
@@ -700,39 +699,6 @@
 /* Position the attr at the correct index */
 #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
 
-/* id_aa64isar1 */
-#define ID_AA64ISAR1_EL1_I8MM_SHIFT		52
-#define ID_AA64ISAR1_EL1_DGH_SHIFT		48
-#define ID_AA64ISAR1_EL1_BF16_SHIFT		44
-#define ID_AA64ISAR1_EL1_SPECRES_SHIFT		40
-#define ID_AA64ISAR1_EL1_SB_SHIFT		36
-#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT		32
-#define ID_AA64ISAR1_EL1_GPI_SHIFT		28
-#define ID_AA64ISAR1_EL1_GPA_SHIFT		24
-#define ID_AA64ISAR1_EL1_LRCPC_SHIFT		20
-#define ID_AA64ISAR1_EL1_FCMA_SHIFT		16
-#define ID_AA64ISAR1_EL1_JSCVT_SHIFT		12
-#define ID_AA64ISAR1_EL1_API_SHIFT		8
-#define ID_AA64ISAR1_EL1_APA_SHIFT		5
-#define ID_AA64ISAR1_EL1_DPB_SHIFT		0
-
-#define ID_AA64ISAR1_EL1_APA_NI			0x0
-#define ID_AA64ISAR1_EL1_APA_PAuth		0x1
-#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC		0x2
-#define ID_AA64ISAR1_EL1_APA_Pauth2		0x3
-#define ID_AA64ISAR1_EL1_APA_FPAC		0x4
-#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE	0x5
-#define ID_AA64ISAR1_EL1_API_NI			0x0
-#define ID_AA64ISAR1_EL1_API_PAuth		0x1
-#define ID_AA64ISAR1_EL1_API_EPAC		0x2
-#define ID_AA64ISAR1_EL1_API_PAuth2		0x3
-#define ID_AA64ISAR1_EL1_API_FPAC		0x4
-#define ID_AA64ISAR1_EL1_API_FPACCOMBINE	0x5
-#define ID_AA64ISAR1_EL1_GPA_NI			0x0
-#define ID_AA64ISAR1_EL1_GPA_IMP		0x1
-#define ID_AA64ISAR1_EL1_GPI_NI			0x0
-#define ID_AA64ISAR1_EL1_GPI_IMP		0x1
-
 /* id_aa64isar2 */
 #define ID_AA64ISAR2_EL1_BC_SHIFT		28
 #define ID_AA64ISAR2_EL1_APA3_SHIFT		12
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index ea3520a347b1..164221177079 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -114,6 +114,89 @@ EndEnum
 Res0	3:0
 EndSysreg
 
+Sysreg	ID_AA64ISAR1_EL1	3	0	0	6	1
+Enum	63:60	LS64
+	0b0000	NI
+	0b0001	LS64
+	0b0010	LS64_V
+	0b0011	LS64_ACCDATA
+EndEnum
+Enum	59:56	XS
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	55:52	I8MM
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	51:48	DGH
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	47:44	BF16
+	0b0000	NI
+	0b0001	IMP
+	0b0010	EBF16
+EndEnum
+Enum	43:40	SPECRES
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	39:36	SB
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	35:32	FRINTTS
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	31:28	GPI
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	27:24	GPA
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	23:20	LRCPC
+	0b0000	NI
+	0b0001	IMP
+	0b0010	LRCPC2
+EndEnum
+Enum	19:16	FCMA
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	15:12	JSCVT
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	11:8	API
+	0b0000	NI
+	0b0001	PAuth
+	0b0010	EPAC
+	0b0011	PAuth2
+	0b0100	FPAC
+	0b0101	FPACCOMBINE
+EndEnum
+Enum	7:4	APA
+	0b0000	NI
+	0b0001	PAuth
+	0b0010	EPAC
+	0b0011	PAuth2
+	0b0100	FPAC
+	0b0101	FPACCOMBINE
+EndEnum
+Enum	3:0	DPB
+	0b0000	NI
+	0b0001	IMP
+	0b0010	DPB2
+EndEnum
+EndSysreg
+	0b0001	IMP
+EndEnum
+EndSysreg
+
 Sysreg	SCTLR_EL1	3	0	1	0	0
 Field	63	TIDCP
 Field	62	SPINMASK
-- 
2.30.2


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  parent reply	other threads:[~2022-06-29 10:48 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-29 10:28 [PATCH v6 00/27] arm64/sysreg: More system register generation Mark Brown
2022-06-29 10:28 ` [PATCH v6 01/27] arm64/cpuinfo: Remove refrences to reserved cache type Mark Brown
2022-07-04 13:04   ` Will Deacon
2022-07-04 15:49     ` Mark Brown
2022-06-29 10:28 ` [PATCH v6 02/27] arm64/sysreg: Allow leading blanks on comments in sysreg file Mark Brown
2022-06-29 10:28 ` [PATCH v6 03/27] arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h Mark Brown
2022-07-04 13:03   ` Will Deacon
2022-07-04 15:28     ` Mark Brown
2022-07-04 16:39       ` Will Deacon
2022-06-29 10:28 ` [PATCH v6 04/27] arm64/sysreg: Add SYS_FIELD_GET() helper Mark Brown
2022-06-29 10:28 ` [PATCH v6 05/27] arm64/sysreg: Standardise naming for CTR_EL0 fields Mark Brown
2022-06-29 10:28 ` [PATCH v6 06/27] arm64/sysreg: Standardise naming for DCZID_EL0 field names Mark Brown
2022-06-29 10:28 ` [PATCH v6 07/27] arm64/mte: Standardise GMID field name definitions Mark Brown
2022-06-29 10:28 ` [PATCH v6 08/27] arm64/sysreg: Align pointer auth enumeration defines with architecture Mark Brown
2022-06-29 10:28 ` [PATCH v6 09/27] arm64/sysreg: Make BHB clear feature defines match the architecture Mark Brown
2022-06-29 10:28 ` [PATCH v6 10/27] arm64/sysreg: Standardise naming for WFxT defines Mark Brown
2022-06-29 10:28 ` [PATCH v6 11/27] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Mark Brown
2022-06-29 10:28 ` [PATCH v6 12/27] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Mark Brown
2022-06-29 10:28 ` [PATCH v6 13/27] arm64/sysreg: Remove defines for RPRES enumeration Mark Brown
2022-06-29 10:28 ` [PATCH v6 14/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Mark Brown
2022-06-29 10:28 ` [PATCH v6 15/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 16/27] arm64/sysreg: Convert CTR_EL0 to automatic generation Mark Brown
2022-06-29 10:28 ` [PATCH v6 17/27] arm64/sysreg: Convert DCZID_EL0 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 18/27] arm64/sysreg: Convert GMID " Mark Brown
2022-06-29 10:28 ` Mark Brown [this message]
2022-06-29 10:28 ` [PATCH v6 20/27] arm64/sysreg: Convert ID_AA64ISAR2_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 21/27] arm64/sysreg: Convert LORSA_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 22/27] arm64/sysreg: Convert LOREA_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 23/27] arm64/sysreg: Convert LORN_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 24/27] arm64/sysreg: Convert LORC_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 25/27] arm64/sysreg: Convert LORID_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 26/27] arm64/sysreg: Convert ID_AA64SMFR0_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 27/27] arm64/sysreg: Convert ID_AA64ZFR0_EL1 " Mark Brown

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