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From: Liu Ying <victor.liu@nxp.com>
To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Cc: andrzej.hajda@intel.com, narmstrong@baylibre.com,
	robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com,
	jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@linux.ie,
	daniel@ffwll.ch, sam@ravnborg.org, marex@denx.de,
	linux-imx@nxp.com
Subject: [PATCH 1/3] drm/bridge: fsl-ldb: Fix mode clock rate validation
Date: Fri,  1 Jul 2022 14:56:32 +0800	[thread overview]
Message-ID: <20220701065634.4027537-2-victor.liu@nxp.com> (raw)
In-Reply-To: <20220701065634.4027537-1-victor.liu@nxp.com>

With LVDS dual link, up to 160MHz mode clock rate is supported.
With LVDS single link, up to 80MHz mode clock rate is supported.
Fix mode clock rate validation by swapping the maximum mode clock
rates of the two link modes.

Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Robert Foss <robert.foss@linaro.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
 drivers/gpu/drm/bridge/fsl-ldb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index b2675c769a55..3cb3b310e283 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -233,7 +233,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge,
 {
 	struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
 
-	if (mode->clock > (fsl_ldb->lvds_dual_link ? 80000 : 160000))
+	if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000))
 		return MODE_CLOCK_HIGH;
 
 	return MODE_OK;
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Liu Ying <victor.liu@nxp.com>
To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Cc: marex@denx.de, jonas@kwiboo.se, airlied@linux.ie,
	robert.foss@linaro.org, narmstrong@baylibre.com,
	jernej.skrabec@gmail.com, Laurent.pinchart@ideasonboard.com,
	andrzej.hajda@intel.com, sam@ravnborg.org, linux-imx@nxp.com
Subject: [PATCH 1/3] drm/bridge: fsl-ldb: Fix mode clock rate validation
Date: Fri,  1 Jul 2022 14:56:32 +0800	[thread overview]
Message-ID: <20220701065634.4027537-2-victor.liu@nxp.com> (raw)
In-Reply-To: <20220701065634.4027537-1-victor.liu@nxp.com>

With LVDS dual link, up to 160MHz mode clock rate is supported.
With LVDS single link, up to 80MHz mode clock rate is supported.
Fix mode clock rate validation by swapping the maximum mode clock
rates of the two link modes.

Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Robert Foss <robert.foss@linaro.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
 drivers/gpu/drm/bridge/fsl-ldb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index b2675c769a55..3cb3b310e283 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -233,7 +233,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge,
 {
 	struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
 
-	if (mode->clock > (fsl_ldb->lvds_dual_link ? 80000 : 160000))
+	if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000))
 		return MODE_CLOCK_HIGH;
 
 	return MODE_OK;
-- 
2.25.1


  reply	other threads:[~2022-07-01  6:55 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-01  6:56 [PATCH 0/3] drm/bridge: fsl-ldb: A few fixes Liu Ying
2022-07-01  6:56 ` Liu Ying
2022-07-01  6:56 ` Liu Ying [this message]
2022-07-01  6:56   ` [PATCH 1/3] drm/bridge: fsl-ldb: Fix mode clock rate validation Liu Ying
2022-07-01  8:02   ` Marek Vasut
2022-07-01  8:02     ` Marek Vasut
2022-07-06 13:34     ` Robert Foss
2022-07-06 13:34       ` Robert Foss
2022-07-07  8:12       ` Neil Armstrong
2022-07-07  8:12         ` Neil Armstrong
2022-07-01  6:56 ` [PATCH 2/3] drm/bridge: fsl-ldb: Enable split mode for LVDS dual link Liu Ying
2022-07-01  6:56   ` Liu Ying
2022-07-01  8:02   ` Marek Vasut
2022-07-01  8:02     ` Marek Vasut
2022-07-01  6:56 ` [PATCH 3/3] drm/bridge: fsl-ldb: Drop DE signal polarity inversion Liu Ying
2022-07-01  6:56   ` Liu Ying
2022-07-01  8:03   ` Marek Vasut
2022-07-01  8:03     ` Marek Vasut
2022-07-04 14:24 ` [PATCH 0/3] drm/bridge: fsl-ldb: A few fixes Neil Armstrong
2022-07-04 14:24   ` Neil Armstrong

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