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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 06/12] drm/i915: Define VBT max HDMI FRL rate bits
Date: Fri, 15 Jul 2022 23:20:38 +0300	[thread overview]
Message-ID: <20220715202044.11153-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220715202044.11153-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The VBT gained some bits to inidicate the max FRL rate for
HDMI 2.1, define them.

These just outright replaced the slave_port bits for ganged eDP.
Apparently that feature was never actually used so someone decided
that reusing the bits is fine. Although the actual ganged eDP
enable bit was still left defined elsewhere for some reason.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index b15e29509fac..8bdb533b5304 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -412,8 +412,10 @@ struct child_device_config {
 			u8 reserved2:3;
 			u8 compression_structure_index:4;	/* 198+ */
 			u8 reserved3:4;
-			u8 slave_port;				/* 202+ */
-			u8 reserved4;
+			u8 hdmi_max_frl_rate:4;			/* 237+ */
+			u8 hdmi_max_frl_rate_valid:1;		/* 237+ */
+			u8 reserved4:3;				/* 237+ */
+			u8 reserved5;
 		} __packed;
 	} __packed;
 
-- 
2.35.1


  parent reply	other threads:[~2022-07-16 14:41 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
2022-07-15 20:20 ` [Intel-gfx] [PATCH 01/12] drm/i915: Unify VBT version number comments Ville Syrjala
2022-07-19 10:25   ` Rodrigo Vivi
2022-09-01  9:24     ` Ville Syrjälä
2022-07-15 20:20 ` [Intel-gfx] [PATCH 02/12] drm/i915: Add some more " Ville Syrjala
2022-09-02 15:00   ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 03/12] drm/i915: Properly define the DP redriver VBT bits Ville Syrjala
2022-09-02 14:45   ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 04/12] drm/i915: Define VBT eDP/DP max lane count bits Ville Syrjala
2022-09-02 14:36   ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 05/12] drm/i915: Add the VBT LTTPR transparent vs. non-transparent bits Ville Syrjala
2022-09-02 14:47   ` Jani Nikula
2022-07-15 20:20 ` Ville Syrjala [this message]
2022-09-02 14:48   ` [Intel-gfx] [PATCH 06/12] drm/i915: Define VBT max HDMI FRL rate bits Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 07/12] drm/i915: Document the sets of bits in the driver features block Ville Syrjala
2022-09-02 14:05   ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 08/12] drm/i915: Define more VBT driver features block bits Ville Syrjala
2022-09-02 14:09   ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define all possible VBT device handles Ville Syrjala
2022-09-02 14:13   ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 10/12] drm/i915: Rename some VBT bits Ville Syrjala
2022-09-02 14:15   ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables Ville Syrjala
2022-07-19 10:31   ` Rodrigo Vivi
2022-09-01  9:24     ` Ville Syrjälä
2022-09-02 14:01   ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 12/12] drm/i915: Parse DP/eDP max lane count from VBT Ville Syrjala
2022-07-19 10:39   ` Rodrigo Vivi
2022-09-01  9:25     ` Ville Syrjälä
2022-09-02 14:42       ` Jani Nikula
2022-07-16 18:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More VBT stuff Patchwork
2022-07-16 21:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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