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From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Openrisc <openrisc@lists.librecores.org>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v3 02/11] target/openrisc: Fix memory reading in debugger
Date: Sat, 30 Jul 2022 08:01:08 +0900	[thread overview]
Message-ID: <20220729230117.3768312-3-shorne@gmail.com> (raw)
In-Reply-To: <20220729230117.3768312-1-shorne@gmail.com>

In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and
instruction TLB reads were combined.  This, broke debugger reads where
we first tried to map using the data tlb then fall back to the
instruction tlb.

This patch replicates this logic by first requesting a PAGE_READ
protection mapping then falling back to PAGE_EXEC.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
Since v2:
 - No changes, added Reviewed-by

 target/openrisc/mmu.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index d7e1320998..0b8afdbacf 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -148,7 +148,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     case SR_DME | SR_IME:
         /* The mmu is definitely enabled.  */
         excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
-                            PAGE_EXEC | PAGE_READ | PAGE_WRITE,
+                            PAGE_READ,
+                            (sr & SR_SM) != 0);
+        if (!excp) {
+            return phys_addr;
+        }
+        excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
+                            PAGE_EXEC,
                             (sr & SR_SM) != 0);
         return excp ? -1 : phys_addr;
 
-- 
2.37.1


WARNING: multiple messages have this Message-ID (diff)
From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Openrisc <openrisc@lists.librecores.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	Stafford Horne <shorne@gmail.com>
Subject: [PATCH v3 02/11] target/openrisc: Fix memory reading in debugger
Date: Sat, 30 Jul 2022 08:01:08 +0900	[thread overview]
Message-ID: <20220729230117.3768312-3-shorne@gmail.com> (raw)
In-Reply-To: <20220729230117.3768312-1-shorne@gmail.com>

In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and
instruction TLB reads were combined.  This, broke debugger reads where
we first tried to map using the data tlb then fall back to the
instruction tlb.

This patch replicates this logic by first requesting a PAGE_READ
protection mapping then falling back to PAGE_EXEC.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
Since v2:
 - No changes, added Reviewed-by

 target/openrisc/mmu.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index d7e1320998..0b8afdbacf 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -148,7 +148,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     case SR_DME | SR_IME:
         /* The mmu is definitely enabled.  */
         excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
-                            PAGE_EXEC | PAGE_READ | PAGE_WRITE,
+                            PAGE_READ,
+                            (sr & SR_SM) != 0);
+        if (!excp) {
+            return phys_addr;
+        }
+        excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
+                            PAGE_EXEC,
                             (sr & SR_SM) != 0);
         return excp ? -1 : phys_addr;
 
-- 
2.37.1



  parent reply	other threads:[~2022-07-29 23:06 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-29 23:01 [PATCH v3 00/11] OpenRISC Virtual Machine Stafford Horne
2022-07-29 23:01 ` Stafford Horne
2022-07-29 23:01 ` [PATCH v3 01/11] hw/openrisc: Split re-usable boot time apis out to boot.c Stafford Horne
2022-07-29 23:01   ` Stafford Horne
2022-07-29 23:01 ` Stafford Horne [this message]
2022-07-29 23:01   ` [PATCH v3 02/11] target/openrisc: Fix memory reading in debugger Stafford Horne
2022-07-29 23:01 ` [PATCH v3 03/11] goldfish_rtc: Add big-endian property Stafford Horne
2022-07-29 23:01   ` Stafford Horne
2022-07-29 23:39   ` Richard Henderson
2022-07-29 23:39     ` Richard Henderson
2022-07-29 23:01 ` [PATCH v3 04/11] hw/openrisc: Add the OpenRISC virtual machine Stafford Horne
2022-07-29 23:01   ` Stafford Horne
2022-07-29 23:01 ` [PATCH v3 05/11] hw/openrisc: Add PCI bus support to virt Stafford Horne
2022-07-29 23:01   ` Stafford Horne
2022-07-29 23:01 ` [PATCH v3 06/11] hw/openrisc: Initialize timer time at startup Stafford Horne
2022-07-29 23:01   ` Stafford Horne
2022-07-29 23:42   ` Richard Henderson
2022-07-29 23:01 ` [PATCH v3 07/11] target/openrisc: Add interrupted CPU to log Stafford Horne
2022-07-29 23:01   ` Stafford Horne
2022-07-29 23:01 ` [PATCH v3 08/11] target/openrisc: Enable MTTCG Stafford Horne
2022-07-29 23:01   ` Stafford Horne
2022-07-29 23:42   ` Richard Henderson
2022-08-02  2:03     ` Stafford Horne
2022-08-02  2:03       ` Stafford Horne
2022-07-29 23:01 ` [PATCH v3 09/11] target/openrisc: Interrupt handling fixes Stafford Horne
2022-07-29 23:01   ` Stafford Horne
2022-07-29 23:01 ` [PATCH v3 10/11] hw/openrisc: virt: pass random seed to fdt Stafford Horne
2022-07-29 23:01   ` Stafford Horne
2022-07-29 23:01 ` [PATCH v3 11/11] docs/system: openrisc: Add OpenRISC documentation Stafford Horne
2022-07-29 23:01   ` Stafford Horne

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