From: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
To: <broonie@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor.dooley@microchip.com>
Cc: <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<Valentina.FernandezAlanis@microchip.com>,
Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Subject: [PATCH v3 4/4] MAINTAINERS: add qspi to Polarfire SoC entry
Date: Fri, 5 Aug 2022 11:00:19 +0530 [thread overview]
Message-ID: <20220805053019.996484-5-nagasuresh.relli@microchip.com> (raw)
In-Reply-To: <20220805053019.996484-1-nagasuresh.relli@microchip.com>
Add the qspi driver to existing Polarfire SoC entry.
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 295ca16a415b..0329dca23fe2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17146,6 +17146,7 @@ S: Supported
F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/soc/microchip/
+F: drivers/spi/spi-microchip-core-qspi.c
F: drivers/spi/spi-microchip-core.c
F: include/soc/microchip/mpfs.h
--
2.25.1
next prev parent reply other threads:[~2022-08-05 5:31 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 5:30 [PATCH v3 0/4] Add support for Microchip QSPI controller Naga Sureshkumar Relli
2022-08-05 5:30 ` [PATCH v3 1/4] spi: dt-binding: document microchip coreQSPI Naga Sureshkumar Relli
2022-08-05 6:46 ` Krzysztof Kozlowski
2022-08-05 5:30 ` [PATCH v3 2/4] spi: dt-binding: add coreqspi as a fallback for mpfs-qspi Naga Sureshkumar Relli
2022-08-05 6:47 ` Krzysztof Kozlowski
2022-08-05 6:49 ` Krzysztof Kozlowski
2022-08-05 7:34 ` Conor.Dooley
2022-08-05 8:12 ` Krzysztof Kozlowski
2022-08-05 8:44 ` Conor.Dooley
2022-08-05 8:47 ` Krzysztof Kozlowski
2022-08-05 14:14 ` Rob Herring
2022-08-05 5:30 ` [PATCH v3 3/4] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers Naga Sureshkumar Relli
2022-08-05 6:50 ` Krzysztof Kozlowski
2022-08-05 5:30 ` Naga Sureshkumar Relli [this message]
2022-08-05 6:50 ` [PATCH v3 4/4] MAINTAINERS: add qspi to Polarfire SoC entry Krzysztof Kozlowski
2022-08-05 11:04 ` Mark Brown
2022-08-05 11:05 ` Mark Brown
2022-08-05 12:07 ` Conor.Dooley
2022-08-05 12:11 ` Mark Brown
2022-08-05 9:14 ` [PATCH v3 0/4] Add support for Microchip QSPI controller Conor.Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220805053019.996484-5-nagasuresh.relli@microchip.com \
--to=nagasuresh.relli@microchip.com \
--cc=Valentina.FernandezAlanis@microchip.com \
--cc=broonie@kernel.org \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.