[PATCH] spi: meson-spicc: save pow2 datarate between messages

[Neil Armstrong <narmstrong@baylibre.com>]

At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(),
this resets the SPICC_CONREG register and notably the value set by the
Common Clock Framework.

This saves the datarate dividor value between message to keep the last
set value by the Common Clock Framework.

This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support")
because we recalculated and wrote the rate for each xfer.

Fixes: 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support")
Reported-by: Da Xue <da@libre.computer>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/spi/spi-meson-spicc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 0bc7daa7afc8..e58686e28439 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -166,6 +166,7 @@ struct meson_spicc_device {
 	unsigned long			tx_remain;
 	unsigned long			rx_remain;
 	unsigned long			xfer_remain;
+	unsigned int			pow2_datarate;
 };
 
 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
@@ -458,7 +459,8 @@ static int meson_spicc_prepare_message(struct spi_master *master,
 	/* Select CS */
 	conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
 
-	/* Default Clock rate core/4 */
+	/* Saved pow2 Clock rate */
+	conf |= FIELD_PREP(SPICC_DATARATE_MASK, spicc->pow2_datarate);
 
 	/* Default 8bit word */
 	conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
@@ -480,6 +482,10 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master)
 	/* Disable all IRQs */
 	writel(0, spicc->base + SPICC_INTREG);
 
+	/* Save last pow2 datarate before HW reset */
+	spicc->pow2_datarate = FIELD_GET(SPICC_DATARATE_MASK,
+					 readl_relaxed(spicc->base + SPICC_CONREG));
+
 	device_reset_optional(&spicc->pdev->dev);
 
 	return 0;
-- 
2.25.1