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From: <tobias.roehmel@rwth-aachen.de>
To: <qemu-devel@nongnu.org>
Cc: peter.maydell@linaro.org,
	"Tobias Röhmel" <tobias.roehmel@rwth-aachen.de>
Subject: [PATCH v3 3/9] target/arm: Make RVBAR available for all ARMv8 CPUs
Date: Sat, 20 Aug 2022 16:19:08 +0200	[thread overview]
Message-ID: <20220820141914.217399-4-tobias.roehmel@rwth-aachen.de> (raw)
In-Reply-To: <20220820141914.217399-1-tobias.roehmel@rwth-aachen.de>

From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>

RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address to be changed with
the rvbar property.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
---
 target/arm/cpu.c    |  6 +++++-
 target/arm/helper.c | 38 ++++++++++++++++++++++++++------------
 2 files changed, 31 insertions(+), 13 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1b5d535788..9007768418 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -258,6 +258,10 @@ static void arm_cpu_reset(DeviceState *dev)
         env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
                                          CPACR, CP11, 3);
 #endif
+        if (arm_feature(env, ARM_FEATURE_V8)) {
+            env->cp15.rvbar = cpu->rvbar_prop;
+            env->regs[15] = cpu->rvbar_prop;
+        }
     }
 
 #if defined(CONFIG_USER_ONLY)
@@ -1273,7 +1277,7 @@ void arm_cpu_post_init(Object *obj)
         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
     }
 
-    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+    if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
         object_property_add_uint64_ptr(obj, "rvbar",
                                        &cpu->rvbar_prop,
                                        OBJ_PROP_FLAG_READWRITE);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b9547594ae..23461397e0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7954,13 +7954,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
         if (!arm_feature(env, ARM_FEATURE_EL3) &&
             !arm_feature(env, ARM_FEATURE_EL2)) {
-            ARMCPRegInfo rvbar = {
-                .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
-                .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
-                .access = PL1_R,
-                .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+            ARMCPRegInfo rvbar[] = {
+                {
+                    .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
+                    .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
+                    .access = PL1_R,
+                    .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+                },
+                {   .name = "RVBAR", .type = ARM_CP_ALIAS,
+                    .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1,
+                    .access = PL1_R,
+                    .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+                },
             };
-            define_one_arm_cp_reg(cpu, &rvbar);
+            define_arm_cp_regs(cpu, rvbar);
         }
         define_arm_cp_regs(cpu, v8_idregs);
         define_arm_cp_regs(cpu, v8_cp_reginfo);
@@ -8022,13 +8029,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         }
         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
         if (!arm_feature(env, ARM_FEATURE_EL3)) {
-            ARMCPRegInfo rvbar = {
-                .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
-                .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
-                .access = PL2_R,
-                .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+            ARMCPRegInfo rvbar[] = {
+                {
+                    .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
+                    .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
+                    .access = PL2_R,
+                    .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+                },
+                {   .name = "RVBAR", .type = ARM_CP_ALIAS,
+                    .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1,
+                    .access = PL2_R,
+                    .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+                },
             };
-            define_one_arm_cp_reg(cpu, &rvbar);
+            define_arm_cp_regs(cpu, rvbar);
         }
     }
 
-- 
2.25.1



  parent reply	other threads:[~2022-08-20 14:30 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-20 14:19 [PATCH v3 0/9] Add ARM Cortex-R52 cpu tobias.roehmel
2022-08-20 14:19 ` [PATCH v3 1/9] target/arm: Add ARM_FEATURE_V8_R tobias.roehmel
2022-08-20 14:19 ` [PATCH v3 2/9] target/arm: Don't add all MIDR aliases for cores that immplement PMSA tobias.roehmel
2022-09-27 16:29   ` Peter Maydell
2022-08-20 14:19 ` tobias.roehmel [this message]
2022-09-27 13:01   ` [PATCH v3 3/9] target/arm: Make RVBAR available for all ARMv8 CPUs Peter Maydell
2022-08-20 14:19 ` [PATCH v3 4/9] target/arm: Make stage_2_format for cache attributes optional tobias.roehmel
2022-09-27 12:52   ` Peter Maydell
2022-08-20 14:19 ` [PATCH v3 5/9] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup tobias.roehmel
2022-09-27 13:05   ` Peter Maydell
2022-08-20 14:19 ` [PATCH v3 6/9] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32 tobias.roehmel
2022-09-27 13:20   ` Peter Maydell
2022-08-20 14:19 ` [PATCH v3 7/9] target/arm: Add PMSAv8r registers tobias.roehmel
2022-09-27 13:50   ` Peter Maydell
2022-10-15 13:07     ` Tobias Roehmel
2022-10-20 15:02       ` Peter Maydell
2022-08-20 14:19 ` [PATCH v3 8/9] target/arm: Add PMSAv8r functionality tobias.roehmel
2022-09-27 16:23   ` Peter Maydell
2022-08-20 14:19 ` [PATCH v3 9/9] target/arm: Add ARM Cortex-R52 cpu tobias.roehmel
2022-09-27 16:31 ` [PATCH v3 0/9] " Peter Maydell

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