From: Rob Clark <robdclark@gmail.com> To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark <robdclark@chromium.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, linux-kernel@vger.kernel.org (open list) Subject: [PATCH 4/5] drm/msm: Use separate ASID for each set of pgtables Date: Sun, 21 Aug 2022 11:19:05 -0700 [thread overview] Message-ID: <20220821181917.1188021-5-robdclark@gmail.com> (raw) In-Reply-To: <20220821181917.1188021-1-robdclark@gmail.com> From: Rob Clark <robdclark@chromium.org> Optimize TLB invalidation by using different ASID for each set of pgtables. There can be scenarios where multiple processes end up with the same ASID (such as >256 processes using the GPU), but this is harmless, it will only result in some over-invalidation (but less over-invalidation compared to using ASID=0 for all processes) Signed-off-by: Rob Clark <robdclark@chromium.org> --- drivers/gpu/drm/msm/msm_iommu.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index a54ed354578b..94c8c09980d1 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -33,6 +33,8 @@ static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, size_t size) { struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); + struct adreno_smmu_priv *adreno_smmu = + dev_get_drvdata(pagetable->parent->dev); struct io_pgtable_ops *ops = pagetable->pgtbl_ops; size_t unmapped = 0; @@ -43,7 +45,7 @@ static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, size -= 4096; } - iommu_flush_iotlb_all(to_msm_iommu(pagetable->parent)->domain); + adreno_smmu->tlb_inv_by_id(adreno_smmu->cookie, pagetable->asid); return (unmapped == size) ? 0 : -EINVAL; } @@ -147,6 +149,7 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) { + static atomic_t asid = ATOMIC_INIT(1); struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev); struct msm_iommu *iommu = to_msm_iommu(parent); struct msm_iommu_pagetable *pagetable; @@ -210,12 +213,14 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; /* - * TODO we would like each set of page tables to have a unique ASID - * to optimize TLB invalidation. But iommu_flush_iotlb_all() will - * end up flushing the ASID used for TTBR1 pagetables, which is not - * what we want. So for now just use the same ASID as TTBR1. + * ASID 0 is used for kernel mapped buffers in TTBR1, which we + * do not need to invalidate when unmapping from TTBR0 pgtables. + * The hw ASID is at *least* 8b, but can be 16b. We just assume + * the worst: */ pagetable->asid = 0; + while (!pagetable->asid) + pagetable->asid = atomic_inc_return(&asid) & 0xff; return &pagetable->base; } -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Rob Clark <robdclark@gmail.com> To: dri-devel@lists.freedesktop.org Cc: Rob Clark <robdclark@chromium.org>, David Airlie <airlied@linux.ie>, linux-arm-msm@vger.kernel.org, Abhinav Kumar <quic_abhinavk@quicinc.com>, open list <linux-kernel@vger.kernel.org>, Sean Paul <sean@poorly.run>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, freedreno@lists.freedesktop.org Subject: [PATCH 4/5] drm/msm: Use separate ASID for each set of pgtables Date: Sun, 21 Aug 2022 11:19:05 -0700 [thread overview] Message-ID: <20220821181917.1188021-5-robdclark@gmail.com> (raw) In-Reply-To: <20220821181917.1188021-1-robdclark@gmail.com> From: Rob Clark <robdclark@chromium.org> Optimize TLB invalidation by using different ASID for each set of pgtables. There can be scenarios where multiple processes end up with the same ASID (such as >256 processes using the GPU), but this is harmless, it will only result in some over-invalidation (but less over-invalidation compared to using ASID=0 for all processes) Signed-off-by: Rob Clark <robdclark@chromium.org> --- drivers/gpu/drm/msm/msm_iommu.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index a54ed354578b..94c8c09980d1 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -33,6 +33,8 @@ static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, size_t size) { struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); + struct adreno_smmu_priv *adreno_smmu = + dev_get_drvdata(pagetable->parent->dev); struct io_pgtable_ops *ops = pagetable->pgtbl_ops; size_t unmapped = 0; @@ -43,7 +45,7 @@ static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, size -= 4096; } - iommu_flush_iotlb_all(to_msm_iommu(pagetable->parent)->domain); + adreno_smmu->tlb_inv_by_id(adreno_smmu->cookie, pagetable->asid); return (unmapped == size) ? 0 : -EINVAL; } @@ -147,6 +149,7 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) { + static atomic_t asid = ATOMIC_INIT(1); struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev); struct msm_iommu *iommu = to_msm_iommu(parent); struct msm_iommu_pagetable *pagetable; @@ -210,12 +213,14 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; /* - * TODO we would like each set of page tables to have a unique ASID - * to optimize TLB invalidation. But iommu_flush_iotlb_all() will - * end up flushing the ASID used for TTBR1 pagetables, which is not - * what we want. So for now just use the same ASID as TTBR1. + * ASID 0 is used for kernel mapped buffers in TTBR1, which we + * do not need to invalidate when unmapping from TTBR0 pgtables. + * The hw ASID is at *least* 8b, but can be 16b. We just assume + * the worst: */ pagetable->asid = 0; + while (!pagetable->asid) + pagetable->asid = atomic_inc_return(&asid) & 0xff; return &pagetable->base; } -- 2.37.2
next prev parent reply other threads:[~2022-08-21 18:19 UTC|newest] Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-21 18:19 [PATCH 0/5] drm/msm+iommu/arm-smmu-qcom: tlbinv optimizations Rob Clark 2022-08-21 18:19 ` Rob Clark 2022-08-21 18:19 ` Rob Clark 2022-08-21 18:19 ` [PATCH 1/5] iommu/arm-smmu-qcom: Fix indentation Rob Clark 2022-08-21 18:19 ` Rob Clark 2022-08-21 18:19 ` [PATCH 2/5] iommu/arm-smmu-qcom: Provide way to access current TTBR0 Rob Clark 2022-08-21 18:19 ` Rob Clark 2022-08-21 18:19 ` Rob Clark 2022-08-21 18:19 ` [PATCH 3/5] iommu/arm-smmu-qcom: Add private interface to tlbinv by ASID Rob Clark 2022-08-21 18:19 ` Rob Clark 2022-08-21 18:19 ` Rob Clark 2022-08-21 18:19 ` Rob Clark [this message] 2022-08-21 18:19 ` [PATCH 4/5] drm/msm: Use separate ASID for each set of pgtables Rob Clark 2022-08-22 13:52 ` Robin Murphy 2022-08-22 13:52 ` Robin Murphy 2022-08-22 14:38 ` Robin Murphy 2022-08-22 14:38 ` Robin Murphy 2022-08-21 18:19 ` [PATCH 5/5] drm/msm: Skip tlbinv on unmap from non-current pgtables Rob Clark 2022-08-21 18:19 ` Rob Clark 2022-08-24 17:46 ` Akhil P Oommen 2022-08-24 17:46 ` Akhil P Oommen 2022-08-24 19:02 ` Rob Clark 2022-08-24 19:02 ` Rob Clark 2022-08-25 18:12 ` Akhil P Oommen 2022-08-25 18:12 ` Akhil P Oommen
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