From: Li Yang <leoyang.li@nxp.com> To: shawnguo@kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>, Li Yang <leoyang.li@nxp.com> Subject: [PATCH 04/11] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Date: Wed, 24 Aug 2022 17:36:55 -0500 [thread overview] Message-ID: <20220824223700.32442-5-leoyang.li@nxp.com> (raw) In-Reply-To: <20220824223700.32442-1-leoyang.li@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> The LS1043A PCIe controller has some control registers in SCFG block, so add the SCFG phandle for each PCIe controller node. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 242fe8bfab17..6b2bfb5c6f32 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -901,6 +901,7 @@ pcie1: pcie@3400000 { <0000 0 0 2 &gic 0 111 0x4>, <0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 4 &gic 0 113 0x4>; + fsl,pcie-scfg = <&scfg 0>; status = "disabled"; }; @@ -927,6 +928,7 @@ pcie2: pcie@3500000 { <0000 0 0 2 &gic 0 121 0x4>, <0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 4 &gic 0 123 0x4>; + fsl,pcie-scfg = <&scfg 1>; status = "disabled"; }; @@ -953,6 +955,7 @@ pcie3: pcie@3600000 { <0000 0 0 2 &gic 0 155 0x4>, <0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 4 &gic 0 157 0x4>; + fsl,pcie-scfg = <&scfg 2>; status = "disabled"; }; -- 2.37.1
WARNING: multiple messages have this Message-ID (diff)
From: Li Yang <leoyang.li@nxp.com> To: shawnguo@kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>, Li Yang <leoyang.li@nxp.com> Subject: [PATCH 04/11] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Date: Wed, 24 Aug 2022 17:36:55 -0500 [thread overview] Message-ID: <20220824223700.32442-5-leoyang.li@nxp.com> (raw) In-Reply-To: <20220824223700.32442-1-leoyang.li@nxp.com> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> The LS1043A PCIe controller has some control registers in SCFG block, so add the SCFG phandle for each PCIe controller node. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 242fe8bfab17..6b2bfb5c6f32 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -901,6 +901,7 @@ pcie1: pcie@3400000 { <0000 0 0 2 &gic 0 111 0x4>, <0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 4 &gic 0 113 0x4>; + fsl,pcie-scfg = <&scfg 0>; status = "disabled"; }; @@ -927,6 +928,7 @@ pcie2: pcie@3500000 { <0000 0 0 2 &gic 0 121 0x4>, <0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 4 &gic 0 123 0x4>; + fsl,pcie-scfg = <&scfg 1>; status = "disabled"; }; @@ -953,6 +955,7 @@ pcie3: pcie@3600000 { <0000 0 0 2 &gic 0 155 0x4>, <0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 4 &gic 0 157 0x4>; + fsl,pcie-scfg = <&scfg 2>; status = "disabled"; }; -- 2.37.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-08-24 22:37 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-24 22:36 [PATCH 00/11] accumulated dts updates for ls1043a Li Yang 2022-08-24 22:36 ` Li Yang 2022-08-24 22:36 ` [PATCH 01/11] arm64: dts: ls1043a: fix the wrong size of dcfg space Li Yang 2022-08-24 22:36 ` Li Yang 2022-08-24 22:36 ` [PATCH 02/11] arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node Li Yang 2022-08-24 22:36 ` Li Yang 2022-08-24 22:36 ` [PATCH 03/11] arm64: dts: ls1043a: use pcie aer/pme interrupts Li Yang 2022-08-24 22:36 ` Li Yang 2022-09-05 1:05 ` Shawn Guo 2022-09-05 1:05 ` Shawn Guo 2022-08-24 22:36 ` Li Yang [this message] 2022-08-24 22:36 ` [PATCH 04/11] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Li Yang 2022-08-24 22:36 ` [PATCH 05/11] arm64: dts: ls1043a: Add big-endian property " Li Yang 2022-08-24 22:36 ` Li Yang 2022-08-24 22:36 ` [PATCH 06/11] arm64: dts: ls1043a: add missing dma ranges property Li Yang 2022-08-24 22:36 ` Li Yang 2022-08-24 22:36 ` [PATCH 07/11] arm64: dts: ls1043a: make dma-coherent global to the SoC Li Yang 2022-08-24 22:36 ` Li Yang 2022-08-24 22:36 ` [PATCH 08/11] arm64: dts: ls1043a: add gpio based i2c recovery information Li Yang 2022-08-24 22:36 ` Li Yang 2022-09-05 1:06 ` Shawn Guo 2022-09-05 1:06 ` Shawn Guo 2022-08-24 22:37 ` [PATCH 09/11] arm64: dts: ls1043a: use a pseudo-bus to constrain usb and sata dma size Li Yang 2022-08-24 22:37 ` Li Yang 2022-09-05 1:09 ` Shawn Guo 2022-09-05 1:09 ` Shawn Guo
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