From: Li Yang <leoyang.li@nxp.com> To: shawnguo@kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Li Yang <leoyang.li@nxp.com>, Camelia Groza <camelia.groza@nxp.com>, Pankaj Bansal <pankaj.bansal@nxp.com> Subject: [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support Date: Wed, 24 Aug 2022 18:11:59 -0500 [thread overview] Message-ID: <20220824231200.494-9-leoyang.li@nxp.com> (raw) In-Reply-To: <20220824231200.494-1-leoyang.li@nxp.com> There is mmio based mdio mux function in the FPGA device on ls1046a-qds board. Add the mmio based mdio-mux nodes to ls1046a-qds boards and add simple-mfd as a compatbile for the FPGA node to reflect the multi-function nature of it. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> --- .../boot/dts/freescale/fsl-ls1046a-qds.dts | 156 +++++++++++++++++- 1 file changed, 154 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts index eec62c63dafe..eb74ed6419b6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -3,7 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * * Shaohui Xie <Shaohui.Xie@nxp.com> */ @@ -25,6 +25,20 @@ aliases { serial1 = &duart1; serial2 = &duart2; serial3 = &duart3; + + emi1-slot1 = &ls1046mdio_s1; + emi1-slot2 = &ls1046mdio_s2; + emi1-slot4 = &ls1046mdio_s4; + + sgmii-s1-p1 = &sgmii_phy_s1_p1; + sgmii-s1-p2 = &sgmii_phy_s1_p2; + sgmii-s1-p3 = &sgmii_phy_s1_p3; + sgmii-s1-p4 = &sgmii_phy_s1_p4; + sgmii-s4-p1 = &sgmii_phy_s4_p1; + qsgmii-s2-p1 = &qsgmii_phy_s2_p1; + qsgmii-s2-p2 = &qsgmii_phy_s2_p2; + qsgmii-s2-p3 = &qsgmii_phy_s2_p3; + qsgmii-s2-p4 = &qsgmii_phy_s2_p4; }; chosen { @@ -153,8 +167,9 @@ nand@1,0 { }; fpga: board-control@2,0 { - compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd"; reg = <0x2 0x0 0x0000100>; + ranges = <0 2 0 0x100>; }; }; @@ -177,3 +192,140 @@ qflash0: flash@0 { }; #include "fsl-ls1046-post.dtsi" + +&fman0 { + ethernet@e0000 { + phy-handle = <&qsgmii_phy_s2_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmii_phy_s4_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&sgmii_phy_s1_p3>; + phy-connection-type = "sgmii"; + }; + + ethernet@ea000 { + phy-handle = <&sgmii_phy_s1_p4>; + phy-connection-type = "sgmii"; + }; + + ethernet@f0000 { /* DTSEC9/10GEC1 */ + phy-handle = <&sgmii_phy_s1_p1>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { /* DTSEC10/10GEC2 */ + phy-handle = <&sgmii_phy_s1_p2>; + phy-connection-type = "xgmii"; + }; +}; + +&fpga { + #address-cells = <1>; + #size-cells = <1>; + mdio-mux-emi1@54 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1 */ + + /* On-board RGMII1 PHY */ + ls1046mdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy1: ethernet-phy@1 { /* MAC3 */ + reg = <0x1>; + }; + }; + + /* On-board RGMII2 PHY */ + ls1046mdio1: mdio@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy2: ethernet-phy@2 { /* MAC4 */ + reg = <0x2>; + }; + }; + + /* Slot 1 */ + ls1046mdio_s1: mdio@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s1_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + + sgmii_phy_s1_p2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy_s1_p3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy_s1_p4: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + + /* Slot 2 */ + ls1046mdio_s2: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + qsgmii_phy_s2_p1: ethernet-phy@8 { + reg = <0x8>; + }; + + qsgmii_phy_s2_p2: ethernet-phy@9 { + reg = <0x9>; + }; + + qsgmii_phy_s2_p3: ethernet-phy@a { + reg = <0xa>; + }; + + qsgmii_phy_s2_p4: ethernet-phy@b { + reg = <0xb>; + }; + }; + + /* Slot 4 */ + ls1046mdio_s4: mdio@80 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s4_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + }; +}; -- 2.37.1
WARNING: multiple messages have this Message-ID (diff)
From: Li Yang <leoyang.li@nxp.com> To: shawnguo@kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Li Yang <leoyang.li@nxp.com>, Camelia Groza <camelia.groza@nxp.com>, Pankaj Bansal <pankaj.bansal@nxp.com> Subject: [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support Date: Wed, 24 Aug 2022 18:11:59 -0500 [thread overview] Message-ID: <20220824231200.494-9-leoyang.li@nxp.com> (raw) In-Reply-To: <20220824231200.494-1-leoyang.li@nxp.com> There is mmio based mdio mux function in the FPGA device on ls1046a-qds board. Add the mmio based mdio-mux nodes to ls1046a-qds boards and add simple-mfd as a compatbile for the FPGA node to reflect the multi-function nature of it. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> --- .../boot/dts/freescale/fsl-ls1046a-qds.dts | 156 +++++++++++++++++- 1 file changed, 154 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts index eec62c63dafe..eb74ed6419b6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -3,7 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * * Shaohui Xie <Shaohui.Xie@nxp.com> */ @@ -25,6 +25,20 @@ aliases { serial1 = &duart1; serial2 = &duart2; serial3 = &duart3; + + emi1-slot1 = &ls1046mdio_s1; + emi1-slot2 = &ls1046mdio_s2; + emi1-slot4 = &ls1046mdio_s4; + + sgmii-s1-p1 = &sgmii_phy_s1_p1; + sgmii-s1-p2 = &sgmii_phy_s1_p2; + sgmii-s1-p3 = &sgmii_phy_s1_p3; + sgmii-s1-p4 = &sgmii_phy_s1_p4; + sgmii-s4-p1 = &sgmii_phy_s4_p1; + qsgmii-s2-p1 = &qsgmii_phy_s2_p1; + qsgmii-s2-p2 = &qsgmii_phy_s2_p2; + qsgmii-s2-p3 = &qsgmii_phy_s2_p3; + qsgmii-s2-p4 = &qsgmii_phy_s2_p4; }; chosen { @@ -153,8 +167,9 @@ nand@1,0 { }; fpga: board-control@2,0 { - compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd"; reg = <0x2 0x0 0x0000100>; + ranges = <0 2 0 0x100>; }; }; @@ -177,3 +192,140 @@ qflash0: flash@0 { }; #include "fsl-ls1046-post.dtsi" + +&fman0 { + ethernet@e0000 { + phy-handle = <&qsgmii_phy_s2_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmii_phy_s4_p1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&sgmii_phy_s1_p3>; + phy-connection-type = "sgmii"; + }; + + ethernet@ea000 { + phy-handle = <&sgmii_phy_s1_p4>; + phy-connection-type = "sgmii"; + }; + + ethernet@f0000 { /* DTSEC9/10GEC1 */ + phy-handle = <&sgmii_phy_s1_p1>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { /* DTSEC10/10GEC2 */ + phy-handle = <&sgmii_phy_s1_p2>; + phy-connection-type = "xgmii"; + }; +}; + +&fpga { + #address-cells = <1>; + #size-cells = <1>; + mdio-mux-emi1@54 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1 */ + + /* On-board RGMII1 PHY */ + ls1046mdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy1: ethernet-phy@1 { /* MAC3 */ + reg = <0x1>; + }; + }; + + /* On-board RGMII2 PHY */ + ls1046mdio1: mdio@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy2: ethernet-phy@2 { /* MAC4 */ + reg = <0x2>; + }; + }; + + /* Slot 1 */ + ls1046mdio_s1: mdio@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s1_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + + sgmii_phy_s1_p2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy_s1_p3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy_s1_p4: ethernet-phy@1f { + reg = <0x1f>; + }; + }; + + /* Slot 2 */ + ls1046mdio_s2: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + qsgmii_phy_s2_p1: ethernet-phy@8 { + reg = <0x8>; + }; + + qsgmii_phy_s2_p2: ethernet-phy@9 { + reg = <0x9>; + }; + + qsgmii_phy_s2_p3: ethernet-phy@a { + reg = <0xa>; + }; + + qsgmii_phy_s2_p4: ethernet-phy@b { + reg = <0xb>; + }; + }; + + /* Slot 4 */ + ls1046mdio_s4: mdio@80 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgmii_phy_s4_p1: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + }; +}; -- 2.37.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-08-24 23:12 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-24 23:11 [PATCH 0/9] accumulated dts updates for ls1046a Li Yang 2022-08-24 23:11 ` Li Yang 2022-08-24 23:11 ` [PATCH 1/9] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node Li Yang 2022-08-24 23:11 ` Li Yang 2022-08-24 23:11 ` [PATCH 2/9] arm64: dts: ls1046a: Add the PME interrupt to PCIe EP nodes Li Yang 2022-08-24 23:11 ` Li Yang 2022-09-05 1:10 ` Shawn Guo 2022-09-05 1:10 ` Shawn Guo 2022-08-24 23:11 ` [PATCH 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes Li Yang 2022-08-24 23:11 ` Li Yang 2022-08-24 23:11 ` [PATCH 4/9] arm64: dts: ls1046a: add missing dma ranges property Li Yang 2022-08-24 23:11 ` Li Yang 2022-08-24 23:11 ` [PATCH 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC Li Yang 2022-08-24 23:11 ` Li Yang 2022-08-24 23:11 ` [PATCH 6/9] arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma size Li Yang 2022-08-24 23:11 ` Li Yang 2022-08-24 23:11 ` [PATCH 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information Li Yang 2022-08-24 23:11 ` Li Yang 2022-09-05 1:12 ` Shawn Guo 2022-09-05 1:12 ` Shawn Guo 2022-08-24 23:11 ` Li Yang [this message] 2022-08-24 23:11 ` [PATCH 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux support Li Yang 2022-09-05 1:17 ` Shawn Guo 2022-09-05 1:17 ` Shawn Guo 2022-08-24 23:12 ` [PATCH 9/9] arm64: dts: ls1046a-qds: Modify the qspi flash frequency Li Yang 2022-08-24 23:12 ` Li Yang
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220824231200.494-9-leoyang.li@nxp.com \ --to=leoyang.li@nxp.com \ --cc=camelia.groza@nxp.com \ --cc=devicetree@vger.kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=pankaj.bansal@nxp.com \ --cc=robh+dt@kernel.org \ --cc=shawnguo@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.