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From: Biju Das <biju.das.jz@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Chris Paterson <chris.paterson2@renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 04/10] dt-bindings: clock: renesas: Document RZ/G2UL SoC
Date: Wed, 31 Aug 2022 17:37:29 +0100	[thread overview]
Message-ID: <20220831163735.2112470-5-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220831163735.2112470-1-biju.das.jz@bp.renesas.com>

commit 3733db1f77130588c9a2c1596937294998bd7d27 upstream.

Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220315142915.17764-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml       | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index bd3af8fc616b..311a93590597 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -10,7 +10,7 @@ maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
 
 description: |
-  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
+  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
   Standby Mode share the same register block.
 
   They provide the following functionalities:
@@ -23,8 +23,9 @@ description: |
 properties:
   compatible:
     enum:
-      - renesas,r9a07g044-cpg  # RZ/G2{L,LC}
-      - renesas,r9a07g054-cpg  # RZ/V2L
+      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
+      - renesas,r9a07g044-cpg # RZ/G2{L,LC}
+      - renesas,r9a07g054-cpg # RZ/V2L
 
   reg:
     maxItems: 1
-- 
2.25.1



  parent reply	other threads:[~2022-08-31 16:37 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-31 16:37 [PATCH 5.10.y-cip 00/10] Document RZ/G2UL SOC bindings Biju Das
2022-08-31 16:37 ` [PATCH 5.10.y-cip 01/10] dt-bindings: arm: renesas: Document Renesas RZ/V2L SoC on SMARC EVK Biju Das
2022-08-31 16:37 ` [PATCH 5.10.y-cip 02/10] dt-bindings: arm: renesas: Document Renesas RZ/G2UL " Biju Das
2022-08-31 16:37 ` [PATCH 5.10.y-cip 03/10] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Biju Das
2022-08-31 16:37 ` Biju Das [this message]
2022-08-31 16:37 ` [PATCH 5.10.y-cip 05/10] dt-bindings: pinctrl: renesas: Document RZ/G2UL pinctrl Biju Das
2022-08-31 16:37 ` [PATCH 5.10.y-cip 06/10] dt-bindings: serial: renesas,scif: Document RZ/G2UL SoC Biju Das
2022-08-31 16:37 ` [PATCH 5.10.y-cip 07/10] dt-bindings: serial: renesas,sci: " Biju Das
2022-08-31 16:37 ` [PATCH 5.10.y-cip 08/10] dt-bindings: dma: rz-dmac: " Biju Das
2022-08-31 16:37 ` [PATCH 5.10.y-cip 09/10] dt-bindings: mmc: renesas,sdhi: " Biju Das
2022-08-31 16:37 ` [PATCH 5.10.y-cip 10/10] dt-bindings: net: renesas,etheravb: " Biju Das
2022-09-02  9:50 ` [PATCH 5.10.y-cip 00/10] Document RZ/G2UL SOC bindings Pavel Machek
2022-09-06  6:28 ` Pavel Machek

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