All of lore.kernel.org
 help / color / mirror / Atom feed
From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Hervé Poussineau" <hpoussin@reactos.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Ani Sinha" <ani@anisinha.ca>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Bernhard Beschow" <shentey@gmail.com>
Subject: [PATCH 27/42] hw/isa/piix4: Allow board to provide PCI interrupt routes
Date: Thu,  1 Sep 2022 18:25:58 +0200	[thread overview]
Message-ID: <20220901162613.6939-28-shentey@gmail.com> (raw)
In-Reply-To: <20220901162613.6939-1-shentey@gmail.com>

PIIX3 initializes the PIRQx route control registers to the default
values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)
April 1997 manual. PIIX4, however, initializes the routes according to
the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to
allow the reset methods to be consolidated, allow board code to specify
the routes.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
 hw/isa/piix4.c  | 14 ++++++++++----
 hw/mips/malta.c |  4 ++++
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index ed9eca715f..763c98b565 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -57,6 +57,8 @@ struct PIIX4State {
     MemoryRegion rcr_mem;
     uint8_t rcr;
 
+    uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS];
+
     bool has_acpi;
     bool has_usb;
     bool smm_enabled;
@@ -122,10 +124,10 @@ static void piix4_isa_reset(DeviceState *dev)
     pci_conf[0x4c] = 0x4d;
     pci_conf[0x4e] = 0x03;
     pci_conf[0x4f] = 0x00;
-    pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
-    pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
-    pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
-    pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
+    pci_conf[PIIX_PIRQCA] = d->pci_irq_reset_mappings[0];
+    pci_conf[PIIX_PIRQCB] = d->pci_irq_reset_mappings[1];
+    pci_conf[PIIX_PIRQCC] = d->pci_irq_reset_mappings[2];
+    pci_conf[PIIX_PIRQCD] = d->pci_irq_reset_mappings[3];
     pci_conf[0x69] = 0x02;
     pci_conf[0x70] = 0x80;
     pci_conf[0x76] = 0x0c;
@@ -299,6 +301,10 @@ static void piix4_init(Object *obj)
 
 static Property piix4_props[] = {
     DEFINE_PROP_UINT32("smb_io_base", PIIX4State, smb_io_base, 0),
+    DEFINE_PROP_UINT8("pirqa", PIIX4State, pci_irq_reset_mappings[0], 0x80),
+    DEFINE_PROP_UINT8("pirqb", PIIX4State, pci_irq_reset_mappings[1], 0x80),
+    DEFINE_PROP_UINT8("pirqc", PIIX4State, pci_irq_reset_mappings[2], 0x80),
+    DEFINE_PROP_UINT8("pirqd", PIIX4State, pci_irq_reset_mappings[3], 0x80),
     DEFINE_PROP_BOOL("has-acpi", PIIX4State, has_acpi, true),
     DEFINE_PROP_BOOL("has-usb", PIIX4State, has_usb, true),
     DEFINE_PROP_BOOL("smm-enabled", PIIX4State, smm_enabled, false),
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 6339b0d66c..44b6b14f3d 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1403,6 +1403,10 @@ void mips_malta_init(MachineState *machine)
     piix4 = pci_new_multifunction(PCI_DEVFN(10, 0), true,
                                   TYPE_PIIX4_PCI_DEVICE);
     qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100);
+    qdev_prop_set_uint8(DEVICE(piix4), "pirqa", 10);
+    qdev_prop_set_uint8(DEVICE(piix4), "pirqb", 10);
+    qdev_prop_set_uint8(DEVICE(piix4), "pirqc", 11);
+    qdev_prop_set_uint8(DEVICE(piix4), "pirqd", 11);
     pci_realize_and_unref(piix4, pci_bus, &error_fatal);
     isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
 
-- 
2.37.3



  parent reply	other threads:[~2022-09-01 16:46 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-01 16:25 [PATCH 00/42] Consolidate PIIX south bridges Bernhard Beschow
2022-09-01 16:25 ` [PATCH 01/42] hw/i386/pc: Create DMA controllers in " Bernhard Beschow
2022-09-01 19:08   ` Philippe Mathieu-Daudé via
2022-09-01 16:25 ` [PATCH 02/42] hw/i386/pc: Create RTC " Bernhard Beschow
2022-09-01 16:25 ` [PATCH 03/42] hw/i386/pc: No need for rtc_state to be an out-parameter Bernhard Beschow
2022-09-01 16:25 ` [PATCH 04/42] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Bernhard Beschow
2022-09-01 16:25 ` [PATCH 05/42] hw/isa/piix3: Create USB controller in host device Bernhard Beschow
2022-09-01 19:13   ` Philippe Mathieu-Daudé via
2022-09-18 21:46     ` Bernhard Beschow
2022-09-01 16:25 ` [PATCH 06/42] hw/isa/piix3: Create power management " Bernhard Beschow
2022-09-01 16:25 ` [PATCH 07/42] hw/intc/i8259: Introduce i8259 proxy "isa-pic" Bernhard Beschow
2022-09-18 19:38   ` Mark Cave-Ayland
2022-09-01 16:25 ` [PATCH 08/42] hw/isa/piix3: Create ISA PIC in host device Bernhard Beschow
2022-09-01 16:25 ` [PATCH 09/42] hw/isa/piix3: Create IDE controller " Bernhard Beschow
2022-09-01 16:25 ` [PATCH 10/42] hw/isa/piix3: Wire up ACPI interrupt internally Bernhard Beschow
2022-09-01 16:25 ` [PATCH 11/42] hw/isa/piix3: Remove extra ';' outside of functions Bernhard Beschow
2022-09-01 20:26   ` [PATCH 11/42] hw/isa/piix3: Remove extra '; ' " Philippe Mathieu-Daudé via
2022-09-01 16:25 ` [PATCH 12/42] hw/isa/piix3: Remove unused include Bernhard Beschow
2022-09-01 16:25 ` [PATCH 13/42] hw/isa/piix3: Add size constraints to rcr_ops Bernhard Beschow
2022-09-01 23:12   ` Philippe Mathieu-Daudé via
2022-09-01 16:25 ` [PATCH 14/42] hw/isa/piix3: Modernize reset handling Bernhard Beschow
2022-09-01 20:33   ` Philippe Mathieu-Daudé via
2022-09-18 19:44   ` Mark Cave-Ayland
2022-09-01 16:25 ` [PATCH 15/42] hw/isa/piix3: Prefer pci_address_space() over get_system_memory() Bernhard Beschow
2022-09-01 20:33   ` Philippe Mathieu-Daudé via
2022-09-01 16:25 ` [PATCH 16/42] hw/isa/piix3: Allow board to provide PCI interrupt routes Bernhard Beschow
2022-09-01 16:25 ` [PATCH 17/42] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Bernhard Beschow
2022-09-01 16:25 ` [PATCH 18/42] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 Bernhard Beschow
2022-09-01 16:25 ` [PATCH 19/42] hw/isa/piix3: Rename piix3_reset() " Bernhard Beschow
2022-09-01 16:25 ` [PATCH 20/42] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_" Bernhard Beschow
2022-09-01 16:25 ` [PATCH 21/42] hw/isa/piix3: Rename typedef PIIX3State to PIIXState Bernhard Beschow
2022-09-01 16:25 ` [PATCH 22/42] hw/mips/malta: Reuse dev variable Bernhard Beschow
2022-09-01 20:53   ` Philippe Mathieu-Daudé via
2022-09-01 16:25 ` [PATCH 23/42] meson: Fix dependencies of piix4 southbridge Bernhard Beschow
2022-09-01 16:25 ` [PATCH 24/42] hw/isa/piix4: Add missing initialization Bernhard Beschow
2022-09-01 16:25 ` [PATCH 25/42] hw/isa/piix4: Move pci_ide_create_devs() call to board code Bernhard Beschow
2022-09-01 20:54   ` Philippe Mathieu-Daudé via
2022-09-01 16:25 ` [PATCH 26/42] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Bernhard Beschow
2022-09-18 20:10   ` Mark Cave-Ayland
2022-09-18 21:47     ` Bernhard Beschow
2022-09-01 16:25 ` Bernhard Beschow [this message]
2022-09-01 20:57   ` [PATCH 27/42] hw/isa/piix4: Allow board to provide PCI interrupt routes Philippe Mathieu-Daudé via
2022-09-01 16:25 ` [PATCH 28/42] hw/isa/piix4: Remove unused code Bernhard Beschow
2022-09-01 16:26 ` [PATCH 29/42] hw/isa/piix4: Use ISA PIC device Bernhard Beschow
2022-09-01 16:26 ` [PATCH 30/42] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Bernhard Beschow
2022-09-01 16:26 ` [PATCH 31/42] hw/isa/piix4: Rename reset control operations to match PIIX3 Bernhard Beschow
2022-09-01 16:26 ` [PATCH 32/42] hw/isa/piix4: Rename wrongly named method Bernhard Beschow
2022-09-01 20:58   ` Philippe Mathieu-Daudé via
2022-09-01 16:26 ` [PATCH 33/42] hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_" Bernhard Beschow
2022-09-01 16:26 ` [PATCH 34/42] hw/isa/piix3: Merge hw/isa/piix4.c Bernhard Beschow
2022-09-01 16:26 ` [PATCH 35/42] hw/isa/piix: Harmonize names of reset control memory regions Bernhard Beschow
2022-09-01 16:26 ` [PATCH 36/42] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Bernhard Beschow
2022-09-01 16:26 ` [PATCH 37/42] hw/isa/piix: Rename functions to be shared for interrupt triggering Bernhard Beschow
2022-09-01 16:26 ` [PATCH 38/42] hw/isa/piix: Consolidate IRQ triggering Bernhard Beschow
2022-09-01 16:26 ` [PATCH 39/42] hw/isa/piix: Unexport PIIXState Bernhard Beschow
2022-09-18 20:21   ` Mark Cave-Ayland
2022-09-18 21:31     ` Bernhard Beschow
2022-09-01 16:26 ` [PATCH 40/42] hw/isa/piix: Share PIIX3 base class with PIIX4 Bernhard Beschow
2022-09-01 16:26 ` [PATCH 41/42] hw/isa/piix: Drop the "3" from the PIIX base class Bernhard Beschow
2022-09-01 16:26 ` [PATCH 42/42] hw/i386/acpi-build: Resolve PIIX ISA bridge rather than ACPI controller Bernhard Beschow
2022-09-01 21:05   ` Philippe Mathieu-Daudé via
2022-09-08 20:30     ` Bernhard Beschow
2022-09-08  8:39 ` [PATCH 00/42] Consolidate PIIX south bridges Bernhard Beschow
2022-09-18 20:22 ` Mark Cave-Ayland
2022-09-18 22:30   ` Bernhard Beschow

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220901162613.6939-28-shentey@gmail.com \
    --to=shentey@gmail.com \
    --cc=ani@anisinha.ca \
    --cc=aurelien@aurel32.net \
    --cc=eduardo@habkost.net \
    --cc=f4bug@amsat.org \
    --cc=hpoussin@reactos.org \
    --cc=imammedo@redhat.com \
    --cc=jiaxun.yang@flygoat.com \
    --cc=marcel.apfelbaum@gmail.com \
    --cc=mst@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.