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From: Sergei Antonov <saproj@gmail.com>
To: linux-mmc@vger.kernel.org
Cc: ulf.hansson@linaro.org, Sergei Antonov <saproj@gmail.com>,
	Jonas Jensen <jonas.jensen@gmail.com>
Subject: [PATCH] mmc: moxart: fix 4-bit bus width, remove 8-bit bus width
Date: Wed,  7 Sep 2022 23:57:53 +0300	[thread overview]
Message-ID: <20220907205753.1577434-1-saproj@gmail.com> (raw)

According to the datasheet:
https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf
, page 377
4-bit bus width is turned on by bit 2 of the Bus Width Register, so
the current bitmask is wrong:
 define BUS_WIDTH_4            BIT(1)
BIT(1) does not work and BIT(2) works. It was verified on real MOXA
hardware with FTSDC010 controller revision 1_6_0.

The corrected value of BUS_WIDTH_4 mask collides with:
 define BUS_WIDTH_8            BIT(2)
No evidence of 8-bit bus width mode is found in the datasheet. Remove
code dealing with 8-bit bus width.

Fixes: 1b66e94e6b99 ("mmc: moxart: Add MOXA ART SD/MMC driver")
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Cc: Jonas Jensen <jonas.jensen@gmail.com>
---
 drivers/mmc/host/moxart-mmc.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/host/moxart-mmc.c b/drivers/mmc/host/moxart-mmc.c
index b6eb75f4bbfc..dfc3ffd5b1f8 100644
--- a/drivers/mmc/host/moxart-mmc.c
+++ b/drivers/mmc/host/moxart-mmc.c
@@ -111,8 +111,8 @@
 #define CLK_DIV_MASK		0x7f
 
 /* REG_BUS_WIDTH */
-#define BUS_WIDTH_8		BIT(2)
-#define BUS_WIDTH_4		BIT(1)
+#define BUS_WIDTH_4_SUPPORT	BIT(3)
+#define BUS_WIDTH_4		BIT(2)
 #define BUS_WIDTH_1		BIT(0)
 
 #define MMC_VDD_360		23
@@ -524,9 +524,6 @@ static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	case MMC_BUS_WIDTH_4:
 		writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);
 		break;
-	case MMC_BUS_WIDTH_8:
-		writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH);
-		break;
 	default:
 		writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);
 		break;
@@ -651,16 +648,8 @@ static int moxart_probe(struct platform_device *pdev)
 		dmaengine_slave_config(host->dma_chan_rx, &cfg);
 	}
 
-	switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) {
-	case 1:
+	if (readl(host->base + REG_BUS_WIDTH) & BUS_WIDTH_4_SUPPORT)
 		mmc->caps |= MMC_CAP_4_BIT_DATA;
-		break;
-	case 2:
-		mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
-		break;
-	default:
-		break;
-	}
 
 	writel(0, host->base + REG_INTERRUPT_MASK);
 
-- 
2.34.1


             reply	other threads:[~2022-09-07 20:58 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-07 20:57 Sergei Antonov [this message]
2022-09-14 14:01 ` [PATCH] mmc: moxart: fix 4-bit bus width, remove 8-bit bus width Ulf Hansson

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