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From: Conor Dooley <conor.dooley@microchip.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Claudiu Beznea <claudiu.beznea@microchip.com>,
	<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	"Rob Herring" <robh@kernel.org>
Subject: [PATCH v5 03/14] dt-bindings: clk: microchip: mpfs: add reset controller support
Date: Fri, 9 Sep 2022 13:31:12 +0100	[thread overview]
Message-ID: <20220909123123.2699583-4-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220909123123.2699583-1-conor.dooley@microchip.com>

The "peripheral" devices on PolarFire SoC can be put into reset, so
update the device tree binding to reflect the presence of a reset
controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../bindings/clock/microchip,mpfs.yaml          | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
index 016a4f378b9b..1d0b6a4fda42 100644
--- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
@@ -40,8 +40,21 @@ properties:
     const: 1
     description: |
       The clock consumer should specify the desired clock by having the clock
-      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
-      for the full list of PolarFire clock IDs.
+      ID in its "clocks" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+
+  resets:
+    maxItems: 1
+
+  '#reset-cells':
+    description:
+      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
+      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
+      peripheral via the clock ID in its "resets" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+    const: 1
 
 required:
   - compatible
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Claudiu Beznea <claudiu.beznea@microchip.com>,
	<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	"Rob Herring" <robh@kernel.org>
Subject: [PATCH v5 03/14] dt-bindings: clk: microchip: mpfs: add reset controller support
Date: Fri, 9 Sep 2022 13:31:12 +0100	[thread overview]
Message-ID: <20220909123123.2699583-4-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220909123123.2699583-1-conor.dooley@microchip.com>

The "peripheral" devices on PolarFire SoC can be put into reset, so
update the device tree binding to reflect the presence of a reset
controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../bindings/clock/microchip,mpfs.yaml          | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
index 016a4f378b9b..1d0b6a4fda42 100644
--- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
@@ -40,8 +40,21 @@ properties:
     const: 1
     description: |
       The clock consumer should specify the desired clock by having the clock
-      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
-      for the full list of PolarFire clock IDs.
+      ID in its "clocks" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+
+  resets:
+    maxItems: 1
+
+  '#reset-cells':
+    description:
+      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
+      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
+      peripheral via the clock ID in its "resets" phandle cell.
+      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
+      PolarFire clock IDs.
+    const: 1
 
 required:
   - compatible
-- 
2.36.1


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  parent reply	other threads:[~2022-09-09 12:32 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-09 12:31 [PATCH v5 00/14] PolarFire SoC reset controller & clock cleanups Conor Dooley
2022-09-09 12:31 ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 01/14] clk: microchip: mpfs: fix clk_cfg array bounds violation Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-12  7:40   ` Claudiu.Beznea
2022-09-12  7:40     ` Claudiu.Beznea
2022-09-29  0:30   ` Stephen Boyd
2022-09-29  0:30     ` Stephen Boyd
2022-09-29  0:32     ` Stephen Boyd
2022-09-29  0:32       ` Stephen Boyd
2022-09-09 12:31 ` [PATCH v5 02/14] clk: microchip: mpfs: make the rtc's ahb clock critical Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` Conor Dooley [this message]
2022-09-09 12:31   ` [PATCH v5 03/14] dt-bindings: clk: microchip: mpfs: add reset controller support Conor Dooley
2022-09-09 12:31 ` [PATCH v5 04/14] clk: microchip: mpfs: add reset controller Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 05/14] reset: add polarfire soc reset support Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 06/14] MAINTAINERS: add polarfire soc reset controller Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 07/14] riscv: dts: microchip: add mpfs specific macb reset support Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2023-03-07 15:16   ` Conor Dooley
2023-03-07 15:16     ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 08/14] clk: microchip: mpfs: add MSS pll's set & round rate Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 09/14] clk: microchip: mpfs: move id & offset out of clock structs Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 10/14] clk: microchip: mpfs: simplify control reg access Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 11/14] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 12/14] clk: microchip: mpfs: convert cfg_clk to clk_divider Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 13/14] clk: microchip: mpfs: convert periph_clk to clk_gate Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:31 ` [PATCH v5 14/14] clk: microchip: mpfs: update module authorship & licencing Conor Dooley
2022-09-09 12:31   ` Conor Dooley
2022-09-09 12:34 ` [PATCH v5 00/14] PolarFire SoC reset controller & clock cleanups Conor.Dooley
2022-09-09 12:34   ` Conor.Dooley

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