[PATCH] mmc: renesas_sdhi: Add margins for main clock and hs clock

From: Biju Das <biju.das.jz@bp.renesas.com>
To: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Wolfram Sang <wsa+renesas@sang-engineering.com>,
	linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH] mmc: renesas_sdhi: Add margins for main clock and hs clock
Date: Tue, 13 Sep 2022 17:15:06 +0100	[thread overview]
Message-ID: <20220913161506.1817432-1-biju.das.jz@bp.renesas.com> (raw)

The SDHI high speed clock is 4 times that of the main clock. Currently,
there is no margin added for setting the rate associated with these
clocks. On RZ/G2L platforms, the lack of these margins leads to the
selection of a clock source with a lower clock rate compared to a higher
one.

RZ/G2L example case:
SD0 hs clock is 533333333 Hz and SD0 main clock is 133333333 Hz.
When we set the rate for the main clock 133333333, the request rate for
the parent becomes 533333332 (133333333 * 4) and the SD0 hs clock is
set as 400000000 Hz.

This patch adds a margin of (1/1024) higher hs clock and main clock rate.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
This patch is tested on RZ/G2{L,UL} platforms. It will be good to test
this patch on RCar Gen3/Gen4 platforms as I don't have the hardware.

Logs:-

Before the change:
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=4266666656
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=2133333328
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=1066666664
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=533333332
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=400000000
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=400000000

After the patch:
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=4270833320
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=2135416660
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=1067708330
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=533854165
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=533333333
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=533333333
 ####rzg2l_cpg_sd_clk_mux_set_parent####### index=0
 ####rzg2l_cpg_sd_clk_mux_determine_rate####### req->rate=533854164
---
 drivers/mmc/host/renesas_sdhi_core.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index 6edbf5c161ab..e41fbfc6ab7d 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -147,6 +147,7 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 	}
 
 	new_clock = wanted_clock << clkh_shift;
+	new_clock += new_clock >> 10;
 
 	/*
 	 * We want the bus clock to be as close as possible to, but no
@@ -172,6 +173,7 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 
 	clk_set_rate(ref_clk, best_freq);
 
+	best_freq += best_freq >> 10;
 	if (priv->clkh)
 		clk_set_rate(priv->clk, best_freq >> clkh_shift);
 
-- 
2.25.1

