From: Anusha Srivatsa <anusha.srivatsa@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/6] drm/i915/display: add cdclk action struct to cdclk_config
Date: Fri, 16 Sep 2022 17:44:00 -0700 [thread overview]
Message-ID: <20220917004404.414981-3-anusha.srivatsa@intel.com> (raw)
In-Reply-To: <20220917004404.414981-1-anusha.srivatsa@intel.com>
The struct has the action to be performed - squash, crawl
or modeset and the corresponding cdclk which is the desired
cdclk. This is the structure that gets populated during
atomic check once it is determined what the cdclk change looks
like
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index c674879a84a5..3869f93e8ad2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -11,13 +11,27 @@
#include "intel_display.h"
#include "intel_global_state.h"
+#define MAX_CDCLK_ACTIONS 1
+
struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc_state;
+enum cdclk_sequence {
+ CDCLK_INVALID_ACTION = -1,
+
+ CDCLK_SQUASH_ONLY = 0,
+ CDCLK_CRAWL_ONLY,
+ CDCLK_LEGACY,
+};
+
struct intel_cdclk_config {
unsigned int cdclk, vco, ref, bypass;
u8 voltage_level;
+ struct cdclk_step {
+ enum cdclk_sequence action;
+ u32 cdclk;
+ } steps[MAX_CDCLK_ACTIONS];
};
struct intel_cdclk_state {
--
2.25.1
next prev parent reply other threads:[~2022-09-17 0:44 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-17 0:43 [Intel-gfx] [PATCH 0/6] Introduce struct cdclk_step Anusha Srivatsa
2022-09-17 0:43 ` [Intel-gfx] [PATCH 1/6] drm/i915/display Add dg2_prog_squash_ctl() helper Anusha Srivatsa
2022-09-17 0:44 ` Anusha Srivatsa [this message]
2022-09-19 9:26 ` [Intel-gfx] [PATCH 2/6] drm/i915/display: add cdclk action struct to cdclk_config Jani Nikula
2022-09-19 19:32 ` Navare, Manasi
2022-09-19 22:42 ` Srivatsa, Anusha
2022-09-20 6:55 ` Jani Nikula
2022-09-17 0:44 ` [Intel-gfx] [PATCH 3/6] drm/i915/display: Embed the new struct steps for squashing Anusha Srivatsa
2022-09-19 9:27 ` Jani Nikula
2022-09-19 19:39 ` Navare, Manasi
2022-09-19 22:54 ` Srivatsa, Anusha
2022-09-17 0:44 ` [Intel-gfx] [PATCH 4/6] drm/i915/display: Embed the new struct steps for crawling Anusha Srivatsa
2022-09-19 9:28 ` Jani Nikula
2022-09-17 0:44 ` [Intel-gfx] [PATCH 5/6] drm/i915/display: Embed the new struct steps for modeset Anusha Srivatsa
2022-09-17 0:44 ` [Intel-gfx] [PATCH 6/6] drm/i915/display: Dump the new cdclk config values Anusha Srivatsa
2022-09-19 19:46 ` Navare, Manasi
2022-09-19 21:10 ` Rodrigo Vivi
2022-09-19 22:35 ` Navare, Manasi
2022-09-20 7:27 ` Jani Nikula
2022-09-20 18:47 ` Srivatsa, Anusha
2022-09-17 1:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce struct cdclk_step Patchwork
2022-09-17 1:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-17 1:35 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-09-17 2:08 ` Dixit, Ashutosh
2022-09-19 6:35 ` Vudum, Lakshminarayana
2022-09-19 16:33 ` Dixit, Ashutosh
2022-09-19 4:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-19 5:42 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-19 6:25 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2022-09-19 19:48 ` [Intel-gfx] [PATCH 0/6] " Navare, Manasi
2022-09-20 8:20 ` Ville Syrjälä
2022-09-20 18:48 ` Srivatsa, Anusha
2022-09-20 21:59 ` Ville Syrjälä
2022-09-23 16:56 ` Srivatsa, Anusha
2022-09-23 19:04 ` Ville Syrjälä
2022-09-26 17:21 ` Srivatsa, Anusha
2022-09-26 17:29 ` Ville Syrjälä
2022-09-26 17:55 ` Srivatsa, Anusha
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