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From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com,
	bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com,
	avagin@gmail.com, seanjc@google.com, chang.seok.bae@intel.com,
	kvm@vger.kernel.org
Subject: [PATCH v2 3/4] x86/fpu: Disallow legacy states from fpstate_clear_xstate_component()
Date: Thu, 22 Sep 2022 13:00:33 -0700	[thread overview]
Message-ID: <20220922200034.23759-4-chang.seok.bae@intel.com> (raw)
In-Reply-To: <20220922200034.23759-1-chang.seok.bae@intel.com>

Commit 087df48c298c ("x86/fpu: Replace KVMs xstate component clearing")
refactored the MPX state clearing code.

But, legacy states are not warranted in this routine:
- It presumes every state is contiguous but that's not true for the legacy
  states. While MXCSR belongs to SSE, the state is located in the XSAVE
  buffer as surrounded by FP states.
- Also, zeroing out legacy states is not meaningful as their init state is
  non-zero.

It is possible to adjust the code to support them. Then, there is no use
for clearing legacy states yet. To make it simple, explicitly disallow
legacy states.

Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Cc: x86@kernel.org
Cc: kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Changes from v1 (Sean Christopherson):
* Revert the name change.
* Add a warning.
* Update title/changelog.
---
 arch/x86/kernel/fpu/xstate.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index d7676cfc32eb..a3f7045d1f8e 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -1375,6 +1375,15 @@ void fpstate_clear_xstate_component(struct fpstate *fps, unsigned int xfeature)
 {
 	void *addr = get_xsave_addr(&fps->regs.xsave, xfeature);
 
+	/*
+	 * Allow extended states only, because:
+	 * (1) Each legacy state is not contiguously located in the buffer.
+	 * (2) Zeroing those states is not meaningful as their init states
+	 *     are not zero.
+	 */
+	if (WARN_ON_ONCE(xfeature <= XFEATURE_SSE))
+		return;
+
 	if (addr)
 		memset(addr, 0, xstate_sizes[xfeature]);
 }
-- 
2.17.1


  parent reply	other threads:[~2022-09-22 20:11 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-22 20:00 [PATCH v2 0/4] x86/fpu: Fix MXCSR handling and SSE component definition Chang S. Bae
2022-09-22 20:00 ` [PATCH v2 1/4] x86/fpu: Fix the MXCSR state reshuffling between userspace and kernel buffers Chang S. Bae
2022-09-22 20:00 ` [PATCH v2 2/4] selftests/x86/mxcsr: Test the MXCSR state write via ptrace Chang S. Bae
2022-09-22 20:00 ` Chang S. Bae [this message]
2022-09-22 20:00 ` [PATCH v2 4/4] x86/fpu: Correct the legacy state offset and size information Chang S. Bae
2022-09-28 21:06   ` Sean Christopherson
2022-09-28 22:16     ` Chang S. Bae
2022-09-28 22:32       ` Sean Christopherson

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