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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH RFC 1/8] clk: renesas: r9a07g044: Add MTU3a clock and reset entry
Date: Mon, 26 Sep 2022 14:21:07 +0100	[thread overview]
Message-ID: <20220926132114.60396-2-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20220926132114.60396-1-biju.das.jz@bp.renesas.com>

Add MTU3a clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index fd7c4eecd398..0c300ce7ebf8 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -182,7 +182,7 @@ static const struct {
 };
 
 static const struct {
-	struct rzg2l_mod_clk common[76];
+	struct rzg2l_mod_clk common[77];
 #ifdef CONFIG_CLK_R9A07G054
 	struct rzg2l_mod_clk drp[0];
 #endif
@@ -204,6 +204,8 @@ static const struct {
 					0x534, 1),
 		DEF_MOD("ostm2_pclk",	R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
 					0x534, 2),
+		DEF_MOD("mtu_x_mck",	R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
+					0x538, 0),
 		DEF_MOD("gpt_pclk",	R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
 					0x540, 0),
 		DEF_MOD("poeg_a_clkp",	R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
@@ -356,6 +358,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
 	DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
 	DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
 	DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
+	DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
 	DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
 	DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
 	DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
-- 
2.25.1


  reply	other threads:[~2022-09-26 14:54 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-26 13:21 [PATCH RFC 0/8] Add RZ/G2L MTU3a MFD and Counter driver Biju Das
2022-09-26 13:21 ` Biju Das [this message]
2022-09-26 13:21 ` [PATCH RFC 2/8] dt-bindings: mfd: Document RZ/G2L MTU3a bindings Biju Das
2022-10-03  7:50   ` Krzysztof Kozlowski
2022-10-03  8:18     ` Biju Das
2022-09-26 13:21 ` [PATCH RFC 3/8] mfd: Add RZ/G2L MTU3 driver Biju Das
2022-09-26 14:24   ` Philipp Zabel
2022-09-27  5:37     ` Biju Das
2022-09-26 13:21 ` [PATCH RFC 4/8] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2UL MTU3 counter Biju Das
2022-10-03  7:53   ` Krzysztof Kozlowski
2022-10-03  8:25     ` Biju Das
2022-09-26 13:21 ` [PATCH RFC 5/8] counter: Add RZ/G2L MTU3 counter driver Biju Das
2022-10-01  0:22   ` William Breathitt Gray
2022-10-05 10:29     ` Biju Das
2022-09-26 13:21 ` [PATCH RFC 6/8] arm64: dts: renesas: r9a07g044: Add MTU3a node Biju Das
2022-09-26 13:21 ` [PATCH RFC 7/8] arm64: dts: renesas: r9a07g054: " Biju Das
2022-09-26 13:21 ` [PATCH RFC 8/8] arm64: dts: renesas: rzg2l-smarc: [HACK] Enable MTU for 16-bit phase count testing Biju Das
2022-09-27 22:05 ` [PATCH RFC 0/8] Add RZ/G2L MTU3a MFD and Counter driver William Breathitt Gray
2022-09-28  6:14   ` Biju Das
2022-09-30 22:57     ` William Breathitt Gray
2022-10-01 16:45       ` Biju Das
2022-10-01 17:05         ` William Breathitt Gray
2022-10-01 17:12           ` Biju Das
2022-10-01 17:43             ` William Breathitt Gray
2022-10-01 18:03               ` Biju Das
2022-10-01 18:34                 ` William Breathitt Gray
2022-10-01 18:51                   ` Biju Das
2022-10-01 19:04                     ` William Breathitt Gray
2022-10-01 19:21                       ` Biju Das

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