From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ravi.kumar.vodapalli@intel.com,
balasubramani.vivekanandan@intel.com,
dri-devel@lists.freedesktop.org
Subject: [PATCH v2 03/14] drm/i915/gt: Drop a few unused register definitions
Date: Fri, 30 Sep 2022 17:45:39 -0700 [thread overview]
Message-ID: <20221001004550.3031431-4-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20221001004550.3031431-1-matthew.d.roper@intel.com>
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 68f45a748712..3a50e8e966aa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -454,13 +454,6 @@
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
-/* GEN9 chicken */
-#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
-#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
-
-#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
-#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
-
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
@@ -967,11 +960,6 @@
#define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
#define GEN7_L3LOG_SIZE 0x80
-#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
-#define PMFLUSHDONE_LNICRSDROP (1 << 20)
-#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
-#define PMFLUSHDONE_LNEBLK (1 << 22)
-
#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
@@ -986,9 +974,6 @@
#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
-#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xb114)
-#define GEN11_I2M_WRITE_DISABLE (1 << 28)
-
#define GEN8_L3SQCREG4 _MMIO(0xb118)
#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
@@ -1191,8 +1176,6 @@
#define SARB_CHICKEN1 _MMIO(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
-#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
-
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
--
2.37.3
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ravi.kumar.vodapalli@intel.com, dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 03/14] drm/i915/gt: Drop a few unused register definitions
Date: Fri, 30 Sep 2022 17:45:39 -0700 [thread overview]
Message-ID: <20221001004550.3031431-4-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20221001004550.3031431-1-matthew.d.roper@intel.com>
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 68f45a748712..3a50e8e966aa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -454,13 +454,6 @@
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
-/* GEN9 chicken */
-#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
-#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
-
-#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
-#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
-
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
@@ -967,11 +960,6 @@
#define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
#define GEN7_L3LOG_SIZE 0x80
-#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
-#define PMFLUSHDONE_LNICRSDROP (1 << 20)
-#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
-#define PMFLUSHDONE_LNEBLK (1 << 22)
-
#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
@@ -986,9 +974,6 @@
#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
-#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xb114)
-#define GEN11_I2M_WRITE_DISABLE (1 << 28)
-
#define GEN8_L3SQCREG4 _MMIO(0xb118)
#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
@@ -1191,8 +1176,6 @@
#define SARB_CHICKEN1 _MMIO(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
-#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
-
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
--
2.37.3
next prev parent reply other threads:[~2022-10-01 0:46 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-01 0:45 [PATCH v2 00/14] Explicit MCR handling and MTL steering Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` [PATCH v2 01/14] drm/i915/gen8: Create separate reg definitions for new MCR registers Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` [PATCH v2 02/14] drm/i915/xehp: " Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` Matt Roper [this message]
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 03/14] drm/i915/gt: Drop a few unused register definitions Matt Roper
2022-10-01 0:45 ` [PATCH v2 04/14] drm/i915/gt: Correct prefix on a few registers Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` [PATCH v2 05/14] drm/i915/gt: Add intel_gt_mcr_multicast_rmw() operation Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` [Intel-gfx] [PATCH v2 06/14] drm/i915/xehp: Check for faults on primary GAM Matt Roper
2022-10-01 0:45 ` Matt Roper
2022-10-01 0:45 ` [PATCH v2 07/14] drm/i915/gt: Add intel_gt_mcr_wait_for_reg_fw() Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` [PATCH v2 08/14] drm/i915: Define MCR registers explicitly Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` [PATCH v2 09/14] drm/i915/gt: Always use MCR functions on multicast registers Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-12 16:18 ` Balasubramani Vivekanandan
2022-10-12 16:18 ` [Intel-gfx] " Balasubramani Vivekanandan
2022-10-01 0:45 ` [PATCH v2 10/14] drm/i915/guc: Handle save/restore of MCR registers explicitly Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` [PATCH v2 11/14] drm/i915/gt: Add MCR-specific workaround initializers Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` [PATCH v2 12/14] drm/i915: Define multicast registers as a new type Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-04 12:56 ` Jani Nikula
2022-10-04 12:56 ` [Intel-gfx] " Jani Nikula
2022-10-04 13:00 ` Jani Nikula
2022-10-04 13:00 ` [Intel-gfx] " Jani Nikula
2022-10-05 1:01 ` Matt Roper
2022-10-05 1:01 ` [Intel-gfx] " Matt Roper
2022-10-13 7:21 ` Balasubramani Vivekanandan
2022-10-13 7:21 ` [Intel-gfx] " Balasubramani Vivekanandan
2022-10-01 0:45 ` [PATCH v2 13/14] drm/i915/mtl: Add multicast steering for render GT Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-14 16:02 ` Balasubramani Vivekanandan
2022-10-14 16:02 ` Balasubramani Vivekanandan
2022-10-14 22:46 ` Matt Roper
2022-10-14 22:46 ` [Intel-gfx] " Matt Roper
2022-10-01 0:45 ` [PATCH v2 14/14] drm/i915/mtl: Add multicast steering for media GT Matt Roper
2022-10-01 0:45 ` [Intel-gfx] " Matt Roper
2022-10-03 8:56 ` Tvrtko Ursulin
2022-10-03 19:32 ` Matt Roper
2022-10-04 10:13 ` Tvrtko Ursulin
2022-10-01 1:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering (rev2) Patchwork
2022-10-01 1:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-01 2:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-01 5:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering (rev3) Patchwork
2022-10-01 5:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-01 5:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-01 21:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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