From: Conor Dooley <conor.dooley@microchip.com> To: "Thierry Reding" <thierry.reding@gmail.com>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org> Cc: Daire McNamara <daire.mcnamara@microchip.com>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-pwm@vger.kernel.org>, <linux-riscv@lists.infradead.org>, Conor Dooley <conor.dooley@microchip.com>, Rob Herring <robh@kernel.org> Subject: [PATCH v11 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Date: Fri, 7 Oct 2022 12:35:10 +0100 [thread overview] Message-ID: <20221007113512.91501-2-conor.dooley@microchip.com> (raw) In-Reply-To: <20221007113512.91501-1-conor.dooley@microchip.com> corePWM is capable of inverted operation but the binding requires \#pwm-cells of 2. Expand the binding to support setting the polarity. Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding") Acked-by: Rob Herring <robh@kernel.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml index a7fae1772a81..cd8e9a8907f8 100644 --- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -30,7 +30,9 @@ properties: maxItems: 1 "#pwm-cells": - const: 2 + enum: [2, 3] + description: + The only flag supported by the controller is PWM_POLARITY_INVERTED. microchip,sync-update-mask: description: | -- 2.37.3
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com> To: "Thierry Reding" <thierry.reding@gmail.com>, "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org> Cc: Daire McNamara <daire.mcnamara@microchip.com>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-pwm@vger.kernel.org>, <linux-riscv@lists.infradead.org>, Conor Dooley <conor.dooley@microchip.com>, Rob Herring <robh@kernel.org> Subject: [PATCH v11 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Date: Fri, 7 Oct 2022 12:35:10 +0100 [thread overview] Message-ID: <20221007113512.91501-2-conor.dooley@microchip.com> (raw) In-Reply-To: <20221007113512.91501-1-conor.dooley@microchip.com> corePWM is capable of inverted operation but the binding requires \#pwm-cells of 2. Expand the binding to support setting the polarity. Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding") Acked-by: Rob Herring <robh@kernel.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml index a7fae1772a81..cd8e9a8907f8 100644 --- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -30,7 +30,9 @@ properties: maxItems: 1 "#pwm-cells": - const: 2 + enum: [2, 3] + description: + The only flag supported by the controller is PWM_POLARITY_INVERTED. microchip,sync-update-mask: description: | -- 2.37.3 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-10-07 11:35 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-07 11:35 [PATCH v11 0/4] Microchip soft ip corePWM driver Conor Dooley 2022-10-07 11:35 ` Conor Dooley 2022-10-07 11:35 ` Conor Dooley [this message] 2022-10-07 11:35 ` [PATCH v11 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Conor Dooley 2022-10-07 11:35 ` [PATCH v11 2/4] riscv: dts: fix the icicle's #pwm-cells Conor Dooley 2022-10-07 11:35 ` Conor Dooley 2022-10-07 11:35 ` [PATCH v11 3/4] pwm: add microchip soft ip corePWM driver Conor Dooley 2022-10-07 11:35 ` Conor Dooley 2022-11-08 15:50 ` Uwe Kleine-König 2022-11-08 15:50 ` Uwe Kleine-König 2022-11-08 18:32 ` Conor Dooley 2022-11-08 18:32 ` Conor Dooley 2022-10-07 11:35 ` [PATCH v11 4/4] MAINTAINERS: add pwm to PolarFire SoC entry Conor Dooley 2022-10-07 11:35 ` Conor Dooley 2022-11-09 9:35 ` Uwe Kleine-König 2022-11-09 9:35 ` Uwe Kleine-König 2022-11-09 10:47 ` Conor Dooley 2022-11-09 10:47 ` Conor Dooley 2022-11-09 21:52 ` (subset) [PATCH v11 0/4] Microchip soft ip corePWM driver Conor Dooley 2022-11-09 21:52 ` Conor Dooley
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20221007113512.91501-2-conor.dooley@microchip.com \ --to=conor.dooley@microchip.com \ --cc=daire.mcnamara@microchip.com \ --cc=devicetree@vger.kernel.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pwm@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=robh+dt@kernel.org \ --cc=robh@kernel.org \ --cc=thierry.reding@gmail.com \ --cc=u.kleine-koenig@pengutronix.de \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.