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From: dthaler1968@googlemail.com
To: bpf@vger.kernel.org
Cc: Dave Thaler <dthaler@microsoft.com>
Subject: [PATCH 2/4] bpf, docs: Fix modulo zero, division by zero, overflow, and underflow
Date: Wed, 19 Oct 2022 18:38:43 +0000	[thread overview]
Message-ID: <20221019183845.905-2-dthaler1968@googlemail.com> (raw)
In-Reply-To: <20221019183845.905-1-dthaler1968@googlemail.com>

From: Dave Thaler <dthaler@microsoft.com>

Fix modulo zero, division by zero, overflow, and underflow.
Also clarify how a negative immediate value is ued in unsigned division

Signed-off-by: Dave Thaler <dthaler@microsoft.com>
---
 Documentation/bpf/instruction-set.rst | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst
index 6847a4cbf..3a64d4b49 100644
--- a/Documentation/bpf/instruction-set.rst
+++ b/Documentation/bpf/instruction-set.rst
@@ -104,19 +104,26 @@ code      value  description
 BPF_ADD   0x00   dst += src
 BPF_SUB   0x10   dst -= src
 BPF_MUL   0x20   dst \*= src
-BPF_DIV   0x30   dst /= src
+BPF_DIV   0x30   dst = (src != 0) ? (dst / src) : 0
 BPF_OR    0x40   dst \|= src
 BPF_AND   0x50   dst &= src
 BPF_LSH   0x60   dst <<= src
 BPF_RSH   0x70   dst >>= src
 BPF_NEG   0x80   dst = ~src
-BPF_MOD   0x90   dst %= src
+BPF_MOD   0x90   dst = (src != 0) ? (dst % src) : dst
 BPF_XOR   0xa0   dst ^= src
 BPF_MOV   0xb0   dst = src
 BPF_ARSH  0xc0   sign extending shift right
 BPF_END   0xd0   byte swap operations (see `Byte swap instructions`_ below)
 ========  =====  ==========================================================
 
+Underflow and overflow are allowed during arithmetic operations,
+meaning the 64-bit or 32-bit value will wrap.  If
+eBPF program execution would result in division by zero,
+the destination register is instead set to zero.
+If execution would result in modulo by zero,
+the destination register is instead left unchanged.
+
 ``BPF_ADD | BPF_X | BPF_ALU`` means::
 
   dst_reg = (u32) dst_reg + (u32) src_reg;
@@ -135,6 +142,10 @@ where '(u32)' indicates truncation to 32 bits.
 
   src_reg = src_reg ^ imm32
 
+Also note that the division and modulo operations are unsigned,
+where 'imm' is first sign extended to 64 bits and then converted
+to an unsigned 64-bit value.  There are no instructions for
+signed division or modulo.
 
 Byte swap instructions
 ~~~~~~~~~~~~~~~~~~~~~~
-- 
2.33.4


  reply	other threads:[~2022-10-19 18:38 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-19 18:38 [PATCH 1/4] bpf, docs: Add note about type convention dthaler1968
2022-10-19 18:38 ` dthaler1968 [this message]
2022-10-19 18:38 ` [PATCH 3/4] bpf, docs: Use consistent names for the same field dthaler1968
2022-10-19 20:57   ` sdf
2022-10-19 21:06     ` Dave Thaler
2022-10-19 23:33       ` Stanislav Fomichev
2022-10-19 23:37         ` Alexei Starovoitov
2022-10-21 17:56           ` Dave Thaler
2022-10-21 18:35             ` Stanislav Fomichev
2022-10-21 19:01             ` Alexei Starovoitov
2022-10-21 19:24               ` Dave Thaler
2022-10-21 20:07                 ` Alexei Starovoitov
2022-10-19 18:38 ` [PATCH 4/4] bpf, docs: Explain helper functions dthaler1968
2022-10-19 20:54   ` sdf
2022-10-27 14:39 [PATCH 1/4] bpf, docs: Add note about type convention dthaler1968
2022-10-27 14:39 ` [PATCH 2/4] bpf, docs: Fix modulo zero, division by zero, overflow, and underflow dthaler1968

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