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From: Swati Sharma <swati2.sharma@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/dsc: Source supports DSC from DISPLAY_VER >= 11
Date: Tue,  1 Nov 2022 13:29:27 +0530	[thread overview]
Message-ID: <20221101075927.15146-1-swati2.sharma@intel.com> (raw)

i915 driver supports DSC from DISPLAY_VER >= 11. Fix it.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7400d6b4c587..02e64f0284d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1012,7 +1012,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	 * Output bpp is stored in 6.4 format so right shift by 4 to get the
 	 * integer value since we support only integer values of bpp.
 	 */
-	if (DISPLAY_VER(dev_priv) >= 10 &&
+	if (DISPLAY_VER(dev_priv) >= 11 &&
 	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 		/*
 		 * TBD pass the connector BPC,
@@ -2906,7 +2906,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
 	intel_dp_set_max_sink_lane_count(intel_dp);
 
 	/* Read the eDP DSC DPCD registers */
-	if (DISPLAY_VER(dev_priv) >= 10)
+	if (DISPLAY_VER(dev_priv) >= 11)
 		intel_dp_get_dsc_sink_cap(intel_dp);
 
 	/*
-- 
2.25.1


             reply	other threads:[~2022-11-01  7:57 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-01  7:59 Swati Sharma [this message]
2022-11-01  8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: Source supports DSC from DISPLAY_VER >= 11 Patchwork
2022-11-01 10:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-11-01 21:20 ` [Intel-gfx] [PATCH] " Matt Roper
2022-11-02  9:02   ` Swati Sharma
2022-11-02  9:32     ` Jani Nikula
2022-11-03  6:05       ` Swati Sharma

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