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From: Bayi Cheng <bayi.cheng@mediatek.com>
To: Mark Brown <broonie@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	<linux-spi@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	Chuanhong Guo <gch981213@gmail.com>,
	<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	Project_Global_Chrome_Upstream_Group 
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	bayi cheng <bayi.cheng@mediatek.com>
Subject: [PATCH v1] spi: spi-mtk-nor: Optimize timeout for dma read
Date: Thu, 3 Nov 2022 13:28:43 +0800	[thread overview]
Message-ID: <20221103052843.2025-2-bayi.cheng@mediatek.com> (raw)
In-Reply-To: <20221103052843.2025-1-bayi.cheng@mediatek.com>

From: bayi cheng <bayi.cheng@mediatek.com>

The timeout value of the current dma read is unreasonable. For example,
If the spi flash clock is 26Mhz, It will takes about 1.3ms to read a
4KB data in spi mode. But the actual measurement exceeds 50s when a
dma read timeout is encountered.

In order to be more accurately, It is necessary to use msecs_to_jiffies,
After modification, the measured timeout value is about 130ms.

Signed-off-by: bayi cheng <bayi.cheng@mediatek.com>
---
 drivers/spi/spi-mtk-nor.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
index d167699a1a96..3d989db80ee9 100644
--- a/drivers/spi/spi-mtk-nor.c
+++ b/drivers/spi/spi-mtk-nor.c
@@ -354,7 +354,7 @@ static int mtk_nor_dma_exec(struct mtk_nor *sp, u32 from, unsigned int length,
 			    dma_addr_t dma_addr)
 {
 	int ret = 0;
-	ulong delay;
+	ulong delay, timeout;
 	u32 reg;
 
 	writel(from, sp->base + MTK_NOR_REG_DMA_FADR);
@@ -376,15 +376,16 @@ static int mtk_nor_dma_exec(struct mtk_nor *sp, u32 from, unsigned int length,
 	mtk_nor_rmw(sp, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
 
 	delay = CLK_TO_US(sp, (length + 5) * BITS_PER_BYTE);
+	timeout = (delay + 1) * 100;
 
 	if (sp->has_irq) {
 		if (!wait_for_completion_timeout(&sp->op_done,
-						 (delay + 1) * 100))
+		    msecs_to_jiffies(max_t(size_t, timeout / 1000, 10))))
 			ret = -ETIMEDOUT;
 	} else {
 		ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg,
 					 !(reg & MTK_NOR_DMA_START), delay / 3,
-					 (delay + 1) * 100);
+					 timeout);
 	}
 
 	if (ret < 0)
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Bayi Cheng <bayi.cheng@mediatek.com>
To: Mark Brown <broonie@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	<linux-spi@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	Chuanhong Guo <gch981213@gmail.com>,
	<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	bayi cheng <bayi.cheng@mediatek.com>
Subject: [PATCH v1] spi: spi-mtk-nor: Optimize timeout for dma read
Date: Thu, 3 Nov 2022 13:28:43 +0800	[thread overview]
Message-ID: <20221103052843.2025-2-bayi.cheng@mediatek.com> (raw)
In-Reply-To: <20221103052843.2025-1-bayi.cheng@mediatek.com>

From: bayi cheng <bayi.cheng@mediatek.com>

The timeout value of the current dma read is unreasonable. For example,
If the spi flash clock is 26Mhz, It will takes about 1.3ms to read a
4KB data in spi mode. But the actual measurement exceeds 50s when a
dma read timeout is encountered.

In order to be more accurately, It is necessary to use msecs_to_jiffies,
After modification, the measured timeout value is about 130ms.

Signed-off-by: bayi cheng <bayi.cheng@mediatek.com>
---
 drivers/spi/spi-mtk-nor.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
index d167699a1a96..3d989db80ee9 100644
--- a/drivers/spi/spi-mtk-nor.c
+++ b/drivers/spi/spi-mtk-nor.c
@@ -354,7 +354,7 @@ static int mtk_nor_dma_exec(struct mtk_nor *sp, u32 from, unsigned int length,
 			    dma_addr_t dma_addr)
 {
 	int ret = 0;
-	ulong delay;
+	ulong delay, timeout;
 	u32 reg;
 
 	writel(from, sp->base + MTK_NOR_REG_DMA_FADR);
@@ -376,15 +376,16 @@ static int mtk_nor_dma_exec(struct mtk_nor *sp, u32 from, unsigned int length,
 	mtk_nor_rmw(sp, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
 
 	delay = CLK_TO_US(sp, (length + 5) * BITS_PER_BYTE);
+	timeout = (delay + 1) * 100;
 
 	if (sp->has_irq) {
 		if (!wait_for_completion_timeout(&sp->op_done,
-						 (delay + 1) * 100))
+		    msecs_to_jiffies(max_t(size_t, timeout / 1000, 10))))
 			ret = -ETIMEDOUT;
 	} else {
 		ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg,
 					 !(reg & MTK_NOR_DMA_START), delay / 3,
-					 (delay + 1) * 100);
+					 timeout);
 	}
 
 	if (ret < 0)
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-11-03  5:29 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-03  5:28 [PATCH v1] spi: spi-mtk-nor: Optimize timeout for dma read Bayi Cheng
2022-11-03  5:28 ` Bayi Cheng
2022-11-03  5:28 ` Bayi Cheng [this message]
2022-11-03  5:28   ` Bayi Cheng
2022-11-03  9:43   ` AngeloGioacchino Del Regno
2022-11-03  9:43     ` AngeloGioacchino Del Regno
2022-11-03 22:35     ` David Laight
2022-11-03 22:35       ` David Laight
2022-11-04  7:53       ` Bayi Cheng (程八意)
2022-11-04  7:53         ` Bayi Cheng (程八意)
2022-11-11  4:16         ` Bayi Cheng (程八意)
2022-11-11  4:16           ` Bayi Cheng (程八意)
2022-11-11  9:16           ` AngeloGioacchino Del Regno
2022-11-11  9:16             ` AngeloGioacchino Del Regno
2022-11-12  6:06             ` Bayi Cheng (程八意)
2022-11-12  6:06               ` Bayi Cheng (程八意)
2022-11-03  5:43 ` Allen-KH Cheng (程冠勳)
2022-11-03  5:43   ` Allen-KH Cheng (程冠勳)

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