All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Jason Wang <jasowang@redhat.com>, Peter Xu <peterx@redhat.com>,
	Yi Liu <yi.l.liu@intel.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>
Subject: [PULL v4 72/83] intel-iommu: drop VTDBus
Date: Mon, 7 Nov 2022 17:53:32 -0500	[thread overview]
Message-ID: <20221107224600.934080-73-mst@redhat.com> (raw)
In-Reply-To: <20221107224600.934080-1-mst@redhat.com>

From: Jason Wang <jasowang@redhat.com>

We introduce VTDBus structure as an intermediate step for searching
the address space. This works well with SID based matching/lookup. But
when we want to support SID plus PASID based address space lookup,
this intermediate steps turns out to be a burden. So the patch simply
drops the VTDBus structure and use the PCIBus and devfn as the key for
the g_hash_table(). This simplifies the codes and the future PASID
extension.

To prevent being slower for past vtd_find_as_from_bus_num() callers, a
vtd_as cache indexed by the bus number is introduced to store the last
recent search result of a vtd_as belongs to a specific bus.

Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221028061436.30093-3-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
 include/hw/i386/intel_iommu.h |  11 +-
 hw/i386/intel_iommu.c         | 234 +++++++++++++++++-----------------
 2 files changed, 118 insertions(+), 127 deletions(-)

diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 67653b0f9b..e49fff2a6c 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -58,7 +58,6 @@ typedef struct VTDContextEntry VTDContextEntry;
 typedef struct VTDContextCacheEntry VTDContextCacheEntry;
 typedef struct VTDAddressSpace VTDAddressSpace;
 typedef struct VTDIOTLBEntry VTDIOTLBEntry;
-typedef struct VTDBus VTDBus;
 typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
 typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
@@ -111,12 +110,6 @@ struct VTDAddressSpace {
     IOVATree *iova_tree;          /* Traces mapped IOVA ranges */
 };
 
-struct VTDBus {
-    PCIBus* bus;		/* A reference to the bus to provide translation for */
-    /* A table of VTDAddressSpace objects indexed by devfn */
-    VTDAddressSpace *dev_as[];
-};
-
 struct VTDIOTLBEntry {
     uint64_t gfn;
     uint16_t domain_id;
@@ -253,8 +246,8 @@ struct IntelIOMMUState {
     uint32_t context_cache_gen;     /* Should be in [1,MAX] */
     GHashTable *iotlb;              /* IOTLB */
 
-    GHashTable *vtd_as_by_busptr;   /* VTDBus objects indexed by PCIBus* reference */
-    VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
+    GHashTable *vtd_address_spaces;             /* VTD address spaces */
+    VTDAddressSpace *vtd_as_cache[VTD_PCI_BUS_MAX]; /* VTD address space cache */
     /* list of registered notifiers */
     QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
 
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 271de995be..3d426bb326 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -61,6 +61,16 @@
     }                                                                         \
 }
 
+/*
+ * PCI bus number (or SID) is not reliable since the device is usaully
+ * initalized before guest can configure the PCI bridge
+ * (SECONDARY_BUS_NUMBER).
+ */
+struct vtd_as_key {
+    PCIBus *bus;
+    uint8_t devfn;
+};
+
 static void vtd_address_space_refresh_all(IntelIOMMUState *s);
 static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n);
 
@@ -210,6 +220,27 @@ static guint vtd_uint64_hash(gconstpointer v)
     return (guint)*(const uint64_t *)v;
 }
 
+static gboolean vtd_as_equal(gconstpointer v1, gconstpointer v2)
+{
+    const struct vtd_as_key *key1 = v1;
+    const struct vtd_as_key *key2 = v2;
+
+    return (key1->bus == key2->bus) && (key1->devfn == key2->devfn);
+}
+
+/*
+ * Note that we use pointer to PCIBus as the key, so hashing/shifting
+ * based on the pointer value is intended. Note that we deal with
+ * collisions through vtd_as_equal().
+ */
+static guint vtd_as_hash(gconstpointer v)
+{
+    const struct vtd_as_key *key = v;
+    guint value = (guint)(uintptr_t)key->bus;
+
+    return (guint)(value << 8 | key->devfn);
+}
+
 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
                                           gpointer user_data)
 {
@@ -248,22 +279,14 @@ static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
 static void vtd_reset_context_cache_locked(IntelIOMMUState *s)
 {
     VTDAddressSpace *vtd_as;
-    VTDBus *vtd_bus;
-    GHashTableIter bus_it;
-    uint32_t devfn_it;
+    GHashTableIter as_it;
 
     trace_vtd_context_cache_reset();
 
-    g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
+    g_hash_table_iter_init(&as_it, s->vtd_address_spaces);
 
-    while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
-        for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
-            vtd_as = vtd_bus->dev_as[devfn_it];
-            if (!vtd_as) {
-                continue;
-            }
-            vtd_as->context_cache_entry.context_cache_gen = 0;
-        }
+    while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_as)) {
+        vtd_as->context_cache_entry.context_cache_gen = 0;
     }
     s->context_cache_gen = 1;
 }
@@ -993,32 +1016,6 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
     return slpte & rsvd_mask;
 }
 
-/* Find the VTD address space associated with a given bus number */
-static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
-{
-    VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
-    GHashTableIter iter;
-
-    if (vtd_bus) {
-        return vtd_bus;
-    }
-
-    /*
-     * Iterate over the registered buses to find the one which
-     * currently holds this bus number and update the bus_num
-     * lookup table.
-     */
-    g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
-    while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
-        if (pci_bus_num(vtd_bus->bus) == bus_num) {
-            s->vtd_as_by_bus_num[bus_num] = vtd_bus;
-            return vtd_bus;
-        }
-    }
-
-    return NULL;
-}
-
 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level
  * of the translation, can be used for deciding the size of large page.
  */
@@ -1632,26 +1629,15 @@ static bool vtd_switch_address_space(VTDAddressSpace *as)
 
 static void vtd_switch_address_space_all(IntelIOMMUState *s)
 {
+    VTDAddressSpace *vtd_as;
     GHashTableIter iter;
-    VTDBus *vtd_bus;
-    int i;
 
-    g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
-    while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
-        for (i = 0; i < PCI_DEVFN_MAX; i++) {
-            if (!vtd_bus->dev_as[i]) {
-                continue;
-            }
-            vtd_switch_address_space(vtd_bus->dev_as[i]);
-        }
+    g_hash_table_iter_init(&iter, s->vtd_address_spaces);
+    while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_as)) {
+        vtd_switch_address_space(vtd_as);
     }
 }
 
-static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
-{
-    return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
-}
-
 static const bool vtd_qualified_faults[] = {
     [VTD_FR_RESERVED] = false,
     [VTD_FR_ROOT_ENTRY_P] = false,
@@ -1686,18 +1672,37 @@ static inline bool vtd_is_interrupt_addr(hwaddr addr)
     return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
 }
 
+static gboolean vtd_find_as_by_sid(gpointer key, gpointer value,
+                                   gpointer user_data)
+{
+    struct vtd_as_key *as_key = (struct vtd_as_key *)key;
+    uint16_t target_sid = *(uint16_t *)user_data;
+    uint16_t sid = PCI_BUILD_BDF(pci_bus_num(as_key->bus), as_key->devfn);
+    return sid == target_sid;
+}
+
+static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)
+{
+    uint8_t bus_num = PCI_BUS_NUM(sid);
+    VTDAddressSpace *vtd_as = s->vtd_as_cache[bus_num];
+
+    if (vtd_as &&
+        (sid == PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn))) {
+        return vtd_as;
+    }
+
+    vtd_as = g_hash_table_find(s->vtd_address_spaces, vtd_find_as_by_sid, &sid);
+    s->vtd_as_cache[bus_num] = vtd_as;
+
+    return vtd_as;
+}
+
 static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
 {
-    VTDBus *vtd_bus;
     VTDAddressSpace *vtd_as;
     bool success = false;
 
-    vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
-    if (!vtd_bus) {
-        goto out;
-    }
-
-    vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)];
+    vtd_as = vtd_get_as_by_sid(s, source_id);
     if (!vtd_as) {
         goto out;
     }
@@ -1733,7 +1738,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
     VTDContextCacheEntry *cc_entry;
     uint64_t slpte, page_mask;
     uint32_t level;
-    uint16_t source_id = vtd_make_source_id(bus_num, devfn);
+    uint16_t source_id = PCI_BUILD_BDF(bus_num, devfn);
     int ret_fr;
     bool is_fpd_set = false;
     bool reads = true;
@@ -1905,11 +1910,10 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
                                           uint16_t source_id,
                                           uint16_t func_mask)
 {
+    GHashTableIter as_it;
     uint16_t mask;
-    VTDBus *vtd_bus;
     VTDAddressSpace *vtd_as;
     uint8_t bus_n, devfn;
-    uint16_t devfn_it;
 
     trace_vtd_inv_desc_cc_devices(source_id, func_mask);
 
@@ -1932,32 +1936,31 @@ static void vtd_context_device_invalidate(IntelIOMMUState *s,
     mask = ~mask;
 
     bus_n = VTD_SID_TO_BUS(source_id);
-    vtd_bus = vtd_find_as_from_bus_num(s, bus_n);
-    if (vtd_bus) {
-        devfn = VTD_SID_TO_DEVFN(source_id);
-        for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
-            vtd_as = vtd_bus->dev_as[devfn_it];
-            if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
-                trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
-                                             VTD_PCI_FUNC(devfn_it));
-                vtd_iommu_lock(s);
-                vtd_as->context_cache_entry.context_cache_gen = 0;
-                vtd_iommu_unlock(s);
-                /*
-                 * Do switch address space when needed, in case if the
-                 * device passthrough bit is switched.
-                 */
-                vtd_switch_address_space(vtd_as);
-                /*
-                 * So a device is moving out of (or moving into) a
-                 * domain, resync the shadow page table.
-                 * This won't bring bad even if we have no such
-                 * notifier registered - the IOMMU notification
-                 * framework will skip MAP notifications if that
-                 * happened.
-                 */
-                vtd_sync_shadow_page_table(vtd_as);
-            }
+    devfn = VTD_SID_TO_DEVFN(source_id);
+
+    g_hash_table_iter_init(&as_it, s->vtd_address_spaces);
+    while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_as)) {
+        if ((pci_bus_num(vtd_as->bus) == bus_n) &&
+            (vtd_as->devfn & mask) == (devfn & mask)) {
+            trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(vtd_as->devfn),
+                                         VTD_PCI_FUNC(vtd_as->devfn));
+            vtd_iommu_lock(s);
+            vtd_as->context_cache_entry.context_cache_gen = 0;
+            vtd_iommu_unlock(s);
+            /*
+             * Do switch address space when needed, in case if the
+             * device passthrough bit is switched.
+             */
+            vtd_switch_address_space(vtd_as);
+            /*
+             * So a device is moving out of (or moving into) a
+             * domain, resync the shadow page table.
+             * This won't bring bad even if we have no such
+             * notifier registered - the IOMMU notification
+             * framework will skip MAP notifications if that
+             * happened.
+             */
+            vtd_sync_shadow_page_table(vtd_as);
         }
     }
 }
@@ -2473,18 +2476,13 @@ static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
 {
     VTDAddressSpace *vtd_dev_as;
     IOMMUTLBEvent event;
-    struct VTDBus *vtd_bus;
     hwaddr addr;
     uint64_t sz;
     uint16_t sid;
-    uint8_t devfn;
     bool size;
-    uint8_t bus_num;
 
     addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
     sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
-    devfn = sid & 0xff;
-    bus_num = sid >> 8;
     size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi);
 
     if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) ||
@@ -2495,12 +2493,11 @@ static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
         return false;
     }
 
-    vtd_bus = vtd_find_as_from_bus_num(s, bus_num);
-    if (!vtd_bus) {
-        goto done;
-    }
-
-    vtd_dev_as = vtd_bus->dev_as[devfn];
+    /*
+     * Using sid is OK since the guest should have finished the
+     * initialization of both the bus and device.
+     */
+    vtd_dev_as = vtd_get_as_by_sid(s, sid);
     if (!vtd_dev_as) {
         goto done;
     }
@@ -3427,27 +3424,27 @@ static const MemoryRegionOps vtd_mem_ir_ops = {
 
 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
 {
-    uintptr_t key = (uintptr_t)bus;
-    VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
+    /*
+     * We can't simply use sid here since the bus number might not be
+     * initialized by the guest.
+     */
+    struct vtd_as_key key = {
+        .bus = bus,
+        .devfn = devfn,
+    };
     VTDAddressSpace *vtd_dev_as;
     char name[128];
 
-    if (!vtd_bus) {
-        uintptr_t *new_key = g_malloc(sizeof(*new_key));
-        *new_key = (uintptr_t)bus;
-        /* No corresponding free() */
-        vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
-                            PCI_DEVFN_MAX);
-        vtd_bus->bus = bus;
-        g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus);
-    }
-
-    vtd_dev_as = vtd_bus->dev_as[devfn];
-
+    vtd_dev_as = g_hash_table_lookup(s->vtd_address_spaces, &key);
     if (!vtd_dev_as) {
+        struct vtd_as_key *new_key = g_malloc(sizeof(*new_key));
+
+        new_key->bus = bus;
+        new_key->devfn = devfn;
+
         snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn),
                  PCI_FUNC(devfn));
-        vtd_bus->dev_as[devfn] = vtd_dev_as = g_new0(VTDAddressSpace, 1);
+        vtd_dev_as = g_new0(VTDAddressSpace, 1);
 
         vtd_dev_as->bus = bus;
         vtd_dev_as->devfn = (uint8_t)devfn;
@@ -3503,6 +3500,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
                                             &vtd_dev_as->nodmar, 0);
 
         vtd_switch_address_space(vtd_dev_as);
+
+        g_hash_table_insert(s->vtd_address_spaces, new_key, vtd_dev_as);
     }
     return vtd_dev_as;
 }
@@ -3881,7 +3880,6 @@ static void vtd_realize(DeviceState *dev, Error **errp)
 
     QLIST_INIT(&s->vtd_as_with_notifiers);
     qemu_mutex_init(&s->iommu_lock);
-    memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
     memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
                           "intel_iommu", DMAR_REG_SIZE);
 
@@ -3903,8 +3901,8 @@ static void vtd_realize(DeviceState *dev, Error **errp)
     /* No corresponding destroy */
     s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
                                      g_free, g_free);
-    s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
-                                              g_free, g_free);
+    s->vtd_address_spaces = g_hash_table_new_full(vtd_as_hash, vtd_as_equal,
+                                      g_free, g_free);
     vtd_init(s);
     sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
     pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
-- 
MST



  parent reply	other threads:[~2022-11-07 23:07 UTC|newest]

Thread overview: 151+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-07 22:47 [PULL v4 00/83] pci,pc,virtio: features, tests, fixes, cleanups Michael S. Tsirkin
2022-11-07 22:47 ` [PULL v4 01/83] hw/i386/e820: remove legacy reserved entries for e820 Michael S. Tsirkin
2022-11-07 22:47 ` [PULL v4 02/83] tests/acpi: allow SSDT changes Michael S. Tsirkin
2022-11-07 22:47 ` [PULL v4 03/83] acpi/ssdt: Fix aml_or() and aml_and() in if clause Michael S. Tsirkin
2022-11-07 22:47 ` [PULL v4 04/83] acpi/nvdimm: define macro for NVDIMM Device _DSM Michael S. Tsirkin
2022-11-07 22:47 ` [PULL v4 05/83] acpi/nvdimm: Implement ACPI NVDIMM Label Methods Michael S. Tsirkin
2022-11-07 22:47 ` [PULL v4 06/83] test/acpi/bios-tables-test: SSDT: update golden master binaries Michael S. Tsirkin
2022-11-07 22:47 ` [PULL v4 07/83] virtio-crypto: Support asynchronous mode Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 08/83] crypto: Support DER encodings Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 09/83] crypto: Support export akcipher to pkcs8 Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 10/83] cryptodev: Add a lkcf-backend for cryptodev Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 11/83] acpi/tests/avocado/bits: initial commit of test scripts that are run by biosbits Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 12/83] acpi/tests/avocado/bits: disable acpi PSS tests that are failing in biosbits Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 13/83] acpi/tests/avocado/bits: add biosbits config file for running bios tests Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 14/83] acpi/tests/avocado/bits: add acpi and smbios avocado tests that uses biosbits Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 15/83] acpi/tests/avocado/bits/doc: add a doc file to describe the acpi bits test Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 16/83] MAINTAINERS: add myself as the maintainer for acpi biosbits avocado tests Michael S. Tsirkin
2022-11-07 22:48 ` [PULL v4 17/83] tests/acpi: virt: allow acpi MADT and FADT changes Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 18/83] acpi: fadt: support revision 6.0 of the ACPI specification Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 19/83] acpi: arm/virt: madt: bump to revision 4 accordingly to ACPI 6.0 Errata A Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 20/83] tests/acpi: virt: update ACPI MADT and FADT binaries Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 21/83] hw/pci: PCIe Data Object Exchange emulation Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 22/83] hw/mem/cxl-type3: Add MSIX support Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 23/83] hw/cxl/cdat: CXL CDAT Data Object Exchange implementation Michael S. Tsirkin
2023-04-11 15:52   ` Peter Maydell
2023-04-12 13:08     ` Jonathan Cameron via
2023-04-12 14:39     ` Jonathan Cameron via
2022-11-07 22:49 ` [PULL v4 24/83] hw/mem/cxl-type3: Add CXL CDAT Data Object Exchange Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 25/83] hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE Michael S. Tsirkin
2023-06-23 13:23   ` Peter Maydell
2022-11-07 22:49 ` [PULL v4 26/83] hw/virtio/virtio-iommu-pci: Enforce the device is plugged on the root bus Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 27/83] virtio: introduce __virtio_queue_reset() Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 28/83] virtio: introduce virtio_queue_reset() Michael S. Tsirkin
2022-11-07 22:49 ` [PULL v4 29/83] virtio: introduce virtio_queue_enable() Michael S. Tsirkin
2022-11-08 19:43   ` Stefan Hajnoczi
2022-11-09  3:31     ` Jason Wang
2022-11-09  6:39       ` Michael S. Tsirkin
2022-11-09  6:48         ` Xuan Zhuo
2022-11-09  7:01           ` Michael S. Tsirkin
2022-11-09  7:11             ` Xuan Zhuo
2022-11-09  6:51       ` Michael S. Tsirkin
2022-11-09  6:55         ` Jason Wang
2022-11-09  6:56           ` Xuan Zhuo
2022-11-09  7:04             ` Michael S. Tsirkin
2022-11-09  7:12               ` Xuan Zhuo
2022-11-09  6:59         ` Michael S. Tsirkin
2022-11-09  8:56           ` Laszlo Ersek
2022-11-09 11:00             ` Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 30/83] virtio: core: vq reset feature negotation support Michael S. Tsirkin
2022-11-18 14:32   ` Stefano Garzarella
2022-11-18 14:39     ` Stefano Garzarella
2022-11-19 17:19     ` Michael S. Tsirkin
2022-11-21  6:17       ` Jason Wang
2022-11-21  7:07         ` Michael S. Tsirkin
2022-11-21  8:20           ` Stefano Garzarella
2022-11-07 22:50 ` [PULL v4 31/83] virtio-pci: support queue reset Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 32/83] virtio-pci: support queue enable Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 33/83] vhost: expose vhost_virtqueue_start() Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 34/83] vhost: expose vhost_virtqueue_stop() Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 35/83] vhost-net: vhost-kernel: introduce vhost_net_virtqueue_reset() Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 36/83] vhost-net: vhost-kernel: introduce vhost_net_virtqueue_restart() Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 37/83] virtio-net: introduce flush_or_purge_queued_packets() Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 38/83] virtio-net: support queue reset Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 39/83] virtio-net: support queue_enable Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 40/83] vhost: vhost-kernel: enable vq reset feature Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 41/83] virtio-net: " Michael S. Tsirkin
2022-11-07 22:50 ` [PULL v4 42/83] virtio-rng-pci: Allow setting nvectors, so we can use MSI-X Michael S. Tsirkin
2023-01-09 10:20   ` Dr. David Alan Gilbert
2023-01-09 10:38     ` Michael S. Tsirkin
2023-01-09 10:43       ` Dr. David Alan Gilbert
2022-11-07 22:51 ` [PULL v4 43/83] vhost-user: Fix out of order vring host notification handling Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 44/83] acpi: pc: vga: use AcpiDevAmlIf interface to build VGA device descriptors Michael S. Tsirkin
2022-11-09 17:39   ` Laurent Vivier
2022-11-09 21:42     ` Michael S. Tsirkin
2022-11-10  9:28       ` Peter Maydell
2022-11-11  9:43         ` Igor Mammedov
2022-11-11 10:25           ` Igor Mammedov
2022-11-10  2:55     ` Ani Sinha
2022-11-07 22:51 ` [PULL v4 45/83] tests: acpi: whitelist DSDT before generating PCI-ISA bridge AML automatically Michael S. Tsirkin
2022-11-08 13:36   ` Igor Mammedov
2022-11-08 13:39     ` Ani Sinha
2022-11-08 14:06       ` Ani Sinha
2022-11-08 13:49     ` Michael S. Tsirkin
2022-11-08 14:31       ` Igor Mammedov
2022-11-07 22:51 ` [PULL v4 46/83] acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML Michael S. Tsirkin
2022-11-17 21:51   ` Volker Rümelin
2022-11-18 13:08     ` Igor Mammedov
2022-11-18 14:55       ` Igor Mammedov
2022-11-19  8:49         ` Volker Rümelin
2022-11-21  7:27           ` Igor Mammedov
2022-11-19 17:22         ` Michael S. Tsirkin
2022-11-21  7:23           ` Igor Mammedov
2022-11-21  7:50             ` Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 47/83] tests: acpi: update expected DSDT after ISA bridge is moved directly under PCI host bridge Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 48/83] tests: acpi: whitelist DSDT before generating ICH9_SMB AML automatically Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 49/83] acpi: add get_dev_aml_func() helper Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 50/83] acpi: enumerate SMB bridge automatically along with other PCI devices Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 51/83] tests: acpi: update expected blobs Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 52/83] tests: acpi: pc/q35 whitelist DSDT before \_GPE cleanup Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 53/83] acpi: pc/35: sanitize _GPE declaration order Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 54/83] tests: acpi: update expected blobs Michael S. Tsirkin
2022-11-07 22:51 ` [PULL v4 55/83] hw/acpi/erst.c: Fix memory handling issues Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 56/83] MAINTAINERS: Add qapi/virtio.json to section "virtio" Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 57/83] msix: Assert that specified vector is in range Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 58/83] hw/i386/pc.c: CXL Fixed Memory Window should not reserve e820 in bios Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 59/83] hw/i386/acpi-build: Remove unused struct Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 60/83] hw/i386/acpi-build: Resolve redundant attribute Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 61/83] hw/i386/acpi-build: Resolve north rather than south bridges Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 62/83] hmat acpi: Don't require initiator value in -numa Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 63/83] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 64/83] tests: acpi: q35: add test for hmat nodes without initiators Michael S. Tsirkin
2022-11-07 22:52 ` [PULL v4 65/83] tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT: Michael S. Tsirkin
2022-11-07 22:53 ` [PULL v4 66/83] tests: Add HMAT AArch64/virt empty table files Michael S. Tsirkin
2022-11-07 22:53 ` [PULL v4 67/83] hw/arm/virt: Enable HMAT on arm virt machine Michael S. Tsirkin
2022-11-07 22:53 ` [PULL v4 68/83] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators Michael S. Tsirkin
2022-11-07 22:53 ` [PULL v4 69/83] tests: virt: Update expected *.acpihmatvirt tables Michael S. Tsirkin
2022-11-07 22:53 ` [PULL v4 70/83] vfio: move implement of vfio_get_xlat_addr() to memory.c Michael S. Tsirkin
2022-11-07 22:53 ` [PULL v4 71/83] intel-iommu: don't warn guest errors when getting rid2pasid entry Michael S. Tsirkin
2022-11-07 22:53 ` Michael S. Tsirkin [this message]
2022-11-07 22:53 ` [PULL v4 73/83] intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function Michael S. Tsirkin
2022-11-07 22:53 ` [PULL v4 74/83] intel-iommu: PASID support Michael S. Tsirkin
2023-04-06 16:22   ` Peter Maydell
2023-04-10  2:55     ` Jason Wang
2022-11-07 22:53 ` [PULL v4 75/83] vhost: Change the sequence of device start Michael S. Tsirkin
2022-11-07 22:53 ` [PULL v4 76/83] vhost-user: Support vhost_dev_start Michael S. Tsirkin
2023-01-06 14:21   ` Laurent Vivier
2023-01-09 10:55     ` Michael S. Tsirkin
2023-01-11  9:50       ` Laurent Vivier
2023-01-12  5:46         ` Yajun Wu
2023-01-12  9:25         ` Maxime Coquelin
2023-01-16  7:14           ` Yajun Wu
2023-01-17  9:49             ` Maxime Coquelin
2023-01-17 12:12               ` Greg Kurz
2023-01-17 12:36                 ` Greg Kurz
2023-01-17 15:07                   ` Maxime Coquelin
2023-01-17 17:55                     ` Greg Kurz
2023-01-17 18:21                       ` Greg Kurz
2023-01-18 11:01                         ` Michael S. Tsirkin
2023-01-19 19:48                   ` Dr. David Alan Gilbert
2022-11-07 22:53 ` [PULL v4 77/83] hw/smbios: add core_count2 to smbios table type 4 Michael S. Tsirkin
2022-11-07 22:54 ` [PULL v4 78/83] bios-tables-test: teach test to use smbios 3.0 tables Michael S. Tsirkin
2022-11-07 22:54 ` [PULL v4 79/83] tests/acpi: allow changes for core_count2 test Michael S. Tsirkin
2022-11-07 22:54 ` [PULL v4 80/83] bios-tables-test: add test for number of cores > 255 Michael S. Tsirkin
2022-11-07 22:54 ` [PULL v4 81/83] tests/acpi: update tables for new core count test Michael S. Tsirkin
2022-11-07 22:54 ` [PULL v4 82/83] hw/virtio: introduce virtio_device_should_start Michael S. Tsirkin
2022-11-07 22:54   ` [Virtio-fs] " Michael S. Tsirkin
2022-11-07 22:54 ` [PULL v4 83/83] checkpatch: better pattern for inline comments Michael S. Tsirkin
2022-11-08  6:23 ` [PULL v4 00/83] pci,pc,virtio: features, tests, fixes, cleanups Michael S. Tsirkin
2022-11-08 13:47   ` Stefan Hajnoczi
2022-11-15 14:01 ` Philippe Mathieu-Daudé
2022-11-16 10:42   ` Igor Mammedov

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221107224600.934080-73-mst@redhat.com \
    --to=mst@redhat.com \
    --cc=eduardo@habkost.net \
    --cc=jasowang@redhat.com \
    --cc=marcel.apfelbaum@gmail.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=peterx@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=yi.l.liu@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.