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From: Robert Hoo <robert.hu@linux.intel.com>
To: pbonzini@redhat.com, seanjc@google.com, kirill.shutemov@linux.intel.com
Cc: kvm@vger.kernel.org, Robert Hoo <robert.hu@linux.intel.com>
Subject: [PATCH v2 8/9] KVM: x86: When guest set CR3, handle LAM bits semantics
Date: Thu, 10 Nov 2022 21:28:47 +0800	[thread overview]
Message-ID: <20221110132848.330793-9-robert.hu@linux.intel.com> (raw)
In-Reply-To: <20221110132848.330793-1-robert.hu@linux.intel.com>

When only changes LAM bits, ask next vcpu run to load mmu pgd, so that it
will build new CR3 with LAM bits updates. No TLB flush needed on this case.
When changes on effective addresses, no matter LAM bits changes or not, go
through normal pgd update process.

Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
---
 arch/x86/kvm/x86.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 5130142fd66d..98890c5506da 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1242,9 +1242,9 @@ static bool kvm_is_valid_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 {
 	bool skip_tlb_flush = false;
-	unsigned long pcid = 0;
+	unsigned long pcid = 0, old_cr3;
 #ifdef CONFIG_X86_64
-	bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
+	bool pcid_enabled = !!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
 
 	if (pcid_enabled) {
 		skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
@@ -1257,6 +1257,10 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 	if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
 		goto handle_tlb_flush;
 
+	if (!guest_cpuid_has(vcpu, X86_FEATURE_LAM) &&
+	    (cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)))
+		return	1;
+
 	/*
 	 * Do not condition the GPA check on long mode, this helper is used to
 	 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
@@ -1268,8 +1272,20 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 	if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
 		return 1;
 
-	if (cr3 != kvm_read_cr3(vcpu))
-		kvm_mmu_new_pgd(vcpu, cr3);
+	old_cr3 = kvm_read_cr3(vcpu);
+	if (cr3 != old_cr3) {
+		if ((cr3 ^ old_cr3) & CR3_ADDR_MASK) {
+			kvm_mmu_new_pgd(vcpu, cr3 & ~(X86_CR3_LAM_U48 |
+					X86_CR3_LAM_U57));
+		} else {
+			/*
+			 * Though effective addr no change, mark the
+			 * request so that LAM bits will take effect
+			 * when enter guest.
+			 */
+			kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
+		}
+	}
 
 	vcpu->arch.cr3 = cr3;
 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
-- 
2.31.1


  parent reply	other threads:[~2022-11-10 13:29 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-10 13:28 [PATCH v2 0/9] Linear Address Masking (LAM) KVM Enabling Robert Hoo
2022-11-10 13:28 ` [PATCH v2 1/9] KVM: x86: Rename cr4_reserved/rsvd_* variables to be more readable Robert Hoo
2022-11-10 13:28 ` [PATCH v2 2/9] KVM: x86: Add CR4.LAM_SUP in guest owned bits Robert Hoo
2022-11-10 13:28 ` [PATCH v2 3/9] KVM: x86: MMU: Rename get_cr3() --> get_pgd() and clear high bits for pgd Robert Hoo
2022-11-10 13:28 ` [PATCH v2 4/9] [Trivial] KVM: x86: MMU: Commets update Robert Hoo
2022-11-10 13:28 ` [PATCH v2 5/9] KVM: x86: MMU: Integrate LAM bits when build guest CR3 Robert Hoo
2022-11-10 13:28 ` [PATCH v2 6/9] KVM: x86: Untag LAM bits when applicable Robert Hoo
2022-11-10 13:28 ` [PATCH v2 7/9] KVM: x86: When judging setting CR3 valid or not, consider LAM bits Robert Hoo
2022-11-10 13:28 ` Robert Hoo [this message]
2022-11-10 13:34   ` [PATCH v2 8/9] KVM: x86: When guest set CR3, handle LAM bits semantics Robert Hoo
2022-11-10 13:28 ` [PATCH v2 9/9] KVM: x86: LAM: Expose LAM CPUID to user space VMM Robert Hoo

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