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From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: f4bug@amsat.org, "Alex Bennée" <alex.bennee@linaro.org>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	kvm@vger.kernel.org (open list:Overall KVM CPUs)
Subject: [PATCH  v5 15/20] hw/i386: update vapic_write to use MemTxAttrs
Date: Fri, 11 Nov 2022 18:25:30 +0000	[thread overview]
Message-ID: <20221111182535.64844-16-alex.bennee@linaro.org> (raw)
In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org>

This allows us to drop the current_cpu hack and properly model an
invalid access to the vapic.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 hw/i386/kvmvapic.c | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 43f8a8f679..a76ed07199 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -635,20 +635,21 @@ static int vapic_prepare(VAPICROMState *s)
     return 0;
 }
 
-static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
-                        unsigned int size)
+static MemTxResult vapic_write(void *opaque, hwaddr addr, uint64_t data,
+                               unsigned int size, MemTxAttrs attrs)
 {
     VAPICROMState *s = opaque;
+    CPUState *cs;
     X86CPU *cpu;
     CPUX86State *env;
     hwaddr rom_paddr;
 
-    if (!current_cpu) {
-        return;
+    if (attrs.requester_type != MTRT_CPU) {
+        return MEMTX_ACCESS_ERROR;
     }
-
-    cpu_synchronize_state(current_cpu);
-    cpu = X86_CPU(current_cpu);
+    cs = qemu_get_cpu(attrs.requester_id);
+    cpu_synchronize_state(cs);
+    cpu = X86_CPU(cs);
     env = &cpu->env;
 
     /*
@@ -708,6 +709,8 @@ static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
         }
         break;
     }
+
+    return MEMTX_OK;
 }
 
 static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size)
@@ -716,7 +719,7 @@ static uint64_t vapic_read(void *opaque, hwaddr addr, unsigned size)
 }
 
 static const MemoryRegionOps vapic_ops = {
-    .write = vapic_write,
+    .write_with_attrs = vapic_write,
     .read = vapic_read,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
-- 
2.34.1


  parent reply	other threads:[~2022-11-11 18:25 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-11 18:25 [PATCH for 8.0 v5 00/20] use MemTxAttrs to avoid current_cpu in hw/ Alex Bennée
2022-11-11 18:25 ` [PATCH v5 01/20] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-11-12  4:18   ` Richard Henderson
2022-11-21 18:32   ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 02/20] target/arm: ensure TCG IO accesses set appropriate MemTxAttrs Alex Bennée
2022-11-12  5:17   ` Richard Henderson
2022-11-12  5:26   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 03/20] target/arm: ensure HVF traps " Alex Bennée
2022-11-11 18:25 ` [PATCH v5 04/20] target/arm: ensure KVM " Alex Bennée
2022-11-11 18:25   ` Alex Bennée
2022-11-12  5:29   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 05/20] target/arm: ensure m-profile helpers " Alex Bennée
2022-11-12  5:26   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 06/20] qtest: make read/write operation appear to be from CPU Alex Bennée
2022-11-11 18:25 ` [PATCH v5 07/20] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-11-11 18:25 ` [PATCH v5 08/20] hw/timer: convert mptimer access to attrs to derive cpu index Alex Bennée
2022-11-11 18:25 ` [PATCH v5 09/20] hw/arm: remove current_cpu hack from pxa2xx access Alex Bennée
2022-11-12  5:36   ` Richard Henderson
2022-11-13 19:43   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 10/20] target/microblaze: initialise MemTxAttrs for CPU access Alex Bennée
2022-11-11 19:41   ` Edgar E. Iglesias
2022-11-12  5:37   ` Richard Henderson
2022-11-13 19:44   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 11/20] target/sparc: " Alex Bennée
2022-11-12  1:02   ` Mark Cave-Ayland
2022-11-12  5:38   ` Richard Henderson
2022-11-13 19:45   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 12/20] target/riscv: " Alex Bennée
2022-11-11 18:25 ` [PATCH v5 13/20] target/i386: add explicit initialisation for MexTxAttrs Alex Bennée
2022-11-11 18:25   ` Alex Bennée
2022-11-12  5:49   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 14/20] hw/audio: explicitly set .requester_type for intel-hda Alex Bennée
2022-11-12  5:50   ` Richard Henderson
2022-11-13 19:50     ` Philippe Mathieu-Daudé
2022-11-21 18:39   ` Peter Maydell
2022-11-21 22:14     ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` Alex Bennée [this message]
2022-11-12  5:51   ` [PATCH v5 15/20] hw/i386: update vapic_write to use MemTxAttrs Richard Henderson
2022-11-13 19:52   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 16/20] include: add MEMTXATTRS_MACHINE helper Alex Bennée
2022-11-12  5:52   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 17/20] hw/intc: properly model IOAPIC MSI messages Alex Bennée
2022-11-12  5:57   ` Richard Henderson
2022-11-11 18:25 ` [PATCH v5 18/20] hw/i386: convert apic access to use MemTxAttrs Alex Bennée
2022-11-12  6:02   ` Richard Henderson
2022-11-21 18:43   ` Peter Maydell
2022-11-11 18:25 ` [PATCH v5 19/20] hw/isa: derive CPUState from MemTxAttrs in apm_ioport_writeb Alex Bennée
2022-11-12  6:04   ` Richard Henderson
2022-11-13 20:04   ` Philippe Mathieu-Daudé
2022-11-11 18:25 ` [PATCH v5 20/20] include/hw: add commentary to current_cpu export Alex Bennée
2022-11-12  6:05   ` Richard Henderson

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