All of lore.kernel.org
 help / color / mirror / Atom feed
From: Weiwei Li <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, bin.meng@windriver.com,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v5 2/9] target/riscv: add support for Zca extension
Date: Fri, 18 Nov 2022 20:37:21 +0800	[thread overview]
Message-ID: <20221118123728.49319-3-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20221118123728.49319-1-liweiwei@iscas.ac.cn>

Modify the check for C extension to Zca (C implies Zca)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
 target/riscv/translate.c                | 8 ++++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 5c69b88d1e..0d73b919ce 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
 
     gen_set_pc(ctx, cpu_pc);
-    if (!has_ext(ctx, RVC)) {
+    if (!ctx->cfg_ptr->ext_zca) {
         TCGv t0 = tcg_temp_new();
 
         misaligned = gen_new_label();
@@ -178,7 +178,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
 
     gen_set_label(l); /* branch taken */
 
-    if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+    if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) {
         /* misaligned */
         gen_exception_inst_addr_mis(ctx);
     } else {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2ab8772ebe..ee24b451e3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -557,7 +557,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 
     /* check misaligned: */
     next_pc = ctx->base.pc_next + imm;
-    if (!has_ext(ctx, RVC)) {
+    if (!ctx->cfg_ptr->ext_zca) {
         if ((next_pc & 0x3) != 0) {
             gen_exception_inst_addr_mis(ctx);
             return;
@@ -1097,7 +1097,11 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
     ctx->virt_inst_excp = false;
     /* Check for compressed insn */
     if (insn_len(opcode) == 2) {
-        if (!has_ext(ctx, RVC)) {
+        /*
+         * Zca support all of the existing C extension, excluding all
+         * compressed floating point loads and stores
+         */
+        if (!ctx->cfg_ptr->ext_zca) {
             gen_exception_illegal(ctx);
         } else {
             ctx->opcode = opcode;
-- 
2.25.1



  parent reply	other threads:[~2022-11-18 12:40 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-18 12:37 [PATCH v5 0/9] support subsets of code size reduction extension Weiwei Li
2022-11-18 12:37 ` [PATCH v5 1/9] target/riscv: add cfg properties for Zc* extension Weiwei Li
2022-11-21  0:57   ` Alistair Francis
2022-11-18 12:37 ` Weiwei Li [this message]
2022-11-21  7:18   ` [PATCH v5 2/9] target/riscv: add support for Zca extension Alistair Francis
2022-11-18 12:37 ` [PATCH v5 3/9] target/riscv: add support for Zcf extension Weiwei Li
2022-11-21  7:19   ` Alistair Francis
2022-11-18 12:37 ` [PATCH v5 4/9] target/riscv: add support for Zcd extension Weiwei Li
2022-11-21  7:20   ` Alistair Francis
2022-11-18 12:37 ` [PATCH v5 5/9] target/riscv: add support for Zcb extension Weiwei Li
2022-11-22  2:10   ` Alistair Francis
2022-11-18 12:37 ` [PATCH v5 6/9] target/riscv: add support for Zcmp extension Weiwei Li
2022-11-22  6:27   ` Alistair Francis
2022-11-18 12:37 ` [PATCH v5 7/9] target/riscv: add support for Zcmt extension Weiwei Li
2022-11-18 18:15   ` Richard Henderson
2022-11-22  6:41   ` Alistair Francis
2022-11-18 12:37 ` [PATCH v5 8/9] target/riscv: expose properties for Zc* extension Weiwei Li
2022-11-18 12:37 ` [PATCH v5 9/9] disas/riscv.c: add disasm support for Zc* Weiwei Li
2022-11-22  2:14   ` Alistair Francis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221118123728.49319-3-liweiwei@iscas.ac.cn \
    --to=liweiwei@iscas.ac.cn \
    --cc=alistair.francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=lazyparser@gmail.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=wangjunqiang@iscas.ac.cn \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.