From: Jisheng Zhang <jszhang@kernel.org> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Jiri Slaby <jirislaby@kernel.org> Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer Date: Sun, 20 Nov 2022 16:21:14 +0800 [thread overview] Message-ID: <20221120082114.3030-8-jszhang@kernel.org> (raw) In-Reply-To: <20221120082114.3030-1-jszhang@kernel.org> I want to maintain this Bouffalolab riscv SoC entry from now on. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 92451834b940..3564b27d7da4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17738,6 +17738,12 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V BOUFFALOLAB SOC SUPPORT +M: Jisheng Zhang <jszhang@kernel.org> +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/bouffalolab/ + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley <conor.dooley@microchip.com> M: Daire McNamara <daire.mcnamara@microchip.com> -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Jiri Slaby <jirislaby@kernel.org> Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer Date: Sun, 20 Nov 2022 16:21:14 +0800 [thread overview] Message-ID: <20221120082114.3030-8-jszhang@kernel.org> (raw) In-Reply-To: <20221120082114.3030-1-jszhang@kernel.org> I want to maintain this Bouffalolab riscv SoC entry from now on. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 92451834b940..3564b27d7da4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17738,6 +17738,12 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V BOUFFALOLAB SOC SUPPORT +M: Jisheng Zhang <jszhang@kernel.org> +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/bouffalolab/ + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley <conor.dooley@microchip.com> M: Daire McNamara <daire.mcnamara@microchip.com> -- 2.37.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-20 8:32 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang 2022-11-20 8:21 ` Jisheng Zhang 2022-11-20 8:21 ` [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Jisheng Zhang 2022-11-20 8:21 ` Jisheng Zhang 2022-11-21 10:08 ` Krzysztof Kozlowski 2022-11-21 10:08 ` Krzysztof Kozlowski 2022-11-30 18:04 ` Rob Herring 2022-11-30 18:04 ` Rob Herring 2022-11-20 8:21 ` [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver Jisheng Zhang 2022-11-20 8:21 ` Jisheng Zhang 2022-11-21 8:09 ` Jiri Slaby 2022-11-21 8:09 ` Jiri Slaby 2022-11-21 13:59 ` Ilpo Järvinen 2022-11-21 13:59 ` Ilpo Järvinen 2022-11-20 8:21 ` [PATCH 3/7] MAINTAINERS: add myself as a reviewer for Bouffalolab uart driver Jisheng Zhang 2022-11-20 8:21 ` Jisheng Zhang 2022-11-20 8:21 ` [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang 2022-11-20 8:21 ` Jisheng Zhang 2022-11-20 10:43 ` Conor Dooley 2022-11-20 10:43 ` Conor Dooley 2022-11-20 8:21 ` [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang 2022-11-20 8:21 ` Jisheng Zhang 2022-11-20 11:02 ` Conor Dooley 2022-11-20 11:02 ` Conor Dooley 2022-11-20 11:58 ` Icenowy Zheng 2022-11-20 11:58 ` Icenowy Zheng 2022-11-20 14:28 ` Conor Dooley 2022-11-20 14:28 ` Conor Dooley 2022-11-20 14:57 ` Emil Renner Berthing 2022-11-20 14:57 ` Emil Renner Berthing 2022-11-20 17:51 ` Conor Dooley 2022-11-20 17:51 ` Conor Dooley 2022-11-20 18:33 ` Emil Renner Berthing 2022-11-20 18:33 ` Emil Renner Berthing 2022-11-21 3:36 ` Icenowy Zheng 2022-11-21 3:36 ` Icenowy Zheng 2022-11-21 11:25 ` Emil Renner Berthing 2022-11-21 11:25 ` Emil Renner Berthing 2022-11-21 10:09 ` Krzysztof Kozlowski 2022-11-21 10:09 ` Krzysztof Kozlowski 2022-11-20 8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang 2022-11-20 8:21 ` Jisheng Zhang 2022-11-20 11:09 ` Conor Dooley 2022-11-20 11:09 ` Conor Dooley 2022-11-20 11:57 ` Icenowy Zheng 2022-11-20 11:57 ` Icenowy Zheng 2022-11-20 15:06 ` Emil Renner Berthing 2022-11-20 15:06 ` Emil Renner Berthing 2022-11-21 10:10 ` Krzysztof Kozlowski 2022-11-21 10:10 ` Krzysztof Kozlowski 2022-11-20 8:21 ` Jisheng Zhang [this message] 2022-11-20 8:21 ` [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer Jisheng Zhang 2022-11-21 10:11 ` Krzysztof Kozlowski 2022-11-21 10:11 ` Krzysztof Kozlowski
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