All of lore.kernel.org
 help / color / mirror / Atom feed
From: Rahul Tanwar <rtanwar@maxlinear.com>
To: Rahul Tanwar <rtanwar@maxlinear.com>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, "Rob Herring" <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Ingo Molnar <mingo@redhat.com>, "Borislav Petkov" <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>, <x86@kernel.org>,
	"H. Peter Anvin" <hpa@zytor.com>, <linux-lgm-soc@maxlinear.com>
Subject: [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic
Date: Thu, 24 Nov 2022 16:41:41 +0800	[thread overview]
Message-ID: <20221124084143.21841-3-rtanwar@maxlinear.com> (raw)
In-Reply-To: <20221124084143.21841-1-rtanwar@maxlinear.com>

Intel defines a few possible interrupt delivery modes. With respect
to boot/init time, mainly two interrupt delivery modes are possible.
PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.

For ACPI or MPS spec compliant systems, it is figured out by some read
only bit field/s available in their respective defined data structures.
But for OF based systems, it is by default set to PIC mode. Presently,
it is hardcoded to legacy PIC mode for OF based x86 systems with no
option to choose the configuration between PIC mode & virtual wire mode.

For this purpose, introduce a new boolean property for interrupt
controller node of lapic which can allow it to be configured to virtual
wire mode as well.

Property name: 'intel,virtual-wire-mode'
Type: Boolean

If not present/not defined, interrupt delivery mode defaults to legacy PIC
mode. If present/defined, interrupt delivery mode is set to virtual wire
mode.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
 .../interrupt-controller/intel,ce4100-lapic.yaml   | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
index 55184cb49432..d2d0145cb889 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml
@@ -39,6 +39,19 @@ properties:
   '#interrupt-cells':
     const: 2
 
+  intel,virtual-wire-mode:
+    description: Intel defines a few possible interrupt delivery
+      modes. With respect to boot/init time, mainly two interrupt
+      delivery modes are possible.
+      PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
+      Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
+      For ACPI or MPS spec compliant systems, it is figured out by some read
+      only bit field/s available in their respective defined data structures.
+      For OF based systems, it is by default set to PIC mode.
+      But if this optional boolean property is set, then the interrupt delivery
+      mode is configured to virtual wire compatibility mode.
+    type: boolean
+
 required:
   - compatible
   - reg
@@ -54,4 +67,5 @@ examples:
         reg = <0xfee00000 0x1000>;
         interrupt-controller;
         #interrupt-cells = <2>;
+        intel,virtual-wire-mode;
     };
-- 
2.17.1


  parent reply	other threads:[~2022-11-24  8:43 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-24  8:41 [PATCH v5 0/4] x86/of: Add support for interrupt mode config for x86 OF systems Rahul Tanwar
2022-11-24  8:41 ` [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Rahul Tanwar
2022-11-30 21:21   ` Rob Herring
2022-12-02 14:04   ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
2022-11-24  8:41 ` Rahul Tanwar [this message]
2022-11-30 21:21   ` [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Rob Herring
2022-12-02 14:03   ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
2022-11-24  8:41 ` [PATCH v5 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Rahul Tanwar
2022-12-02 14:03   ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
2022-11-24  8:41 ` [PATCH v5 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Rahul Tanwar
2022-12-02 14:03   ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221124084143.21841-3-rtanwar@maxlinear.com \
    --to=rtanwar@maxlinear.com \
    --cc=andriy.shevchenko@linux.intel.com \
    --cc=bp@alien8.de \
    --cc=dave.hansen@linux.intel.com \
    --cc=devicetree@vger.kernel.org \
    --cc=hpa@zytor.com \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-lgm-soc@maxlinear.com \
    --cc=maz@kernel.org \
    --cc=mingo@redhat.com \
    --cc=robh+dt@kernel.org \
    --cc=tglx@linutronix.de \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.