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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, bin.meng@windriver.com,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v7 8/9] target/riscv: expose properties for Zc* extension
Date: Tue, 29 Nov 2022 10:43:42 +0800	[thread overview]
Message-ID: <20221129024343.20384-9-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20221129024343.20384-1-liweiwei@iscas.ac.cn>

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3d06b57416..5f03698b3b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -81,6 +81,12 @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
     ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
     ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
+    ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca),
+    ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
+    ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
+    ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
+    ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
+    ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
     ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
     ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
     ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
@@ -1116,6 +1122,13 @@ static Property riscv_cpu_extensions[] = {
 
     /* These are experimental so mark with 'x-' */
     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+
+    DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
+    DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
+    DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
+    DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
+    DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
+    DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
     /* ePMP 0.9.3 */
     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
     DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
-- 
2.25.1



  parent reply	other threads:[~2022-11-29  2:46 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-29  2:43 [PATCH v7 0/9] support subsets of code size reduction extension Weiwei Li
2022-11-29  2:43 ` [PATCH v7 1/9] target/riscv: add cfg properties for Zc* extension Weiwei Li
2022-11-29  2:43 ` [PATCH v7 2/9] target/riscv: add support for Zca extension Weiwei Li
2022-11-29  2:43 ` [PATCH v7 3/9] target/riscv: add support for Zcf extension Weiwei Li
2022-11-29  2:43 ` [PATCH v7 4/9] target/riscv: add support for Zcd extension Weiwei Li
2022-11-29  2:43 ` [PATCH v7 5/9] target/riscv: add support for Zcb extension Weiwei Li
2022-11-29  2:43 ` [PATCH v7 6/9] target/riscv: add support for Zcmp extension Weiwei Li
2022-11-29  2:43 ` [PATCH v7 7/9] target/riscv: add support for Zcmt extension Weiwei Li
2022-11-29  2:43 ` Weiwei Li [this message]
2022-11-29  2:43 ` [PATCH v7 9/9] disas/riscv.c: add disasm support for Zc* Weiwei Li
2022-11-30  3:04   ` Shaobo Song
2022-11-30  7:08     ` [PATCH " weiwei
2022-11-30  5:38   ` Shaobo Song

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