From: Anup Patel <apatel@ventanamicro.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Atish Patra <atishp@atishpatra.org>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>, Bin Meng <bmeng.cn@gmail.com>, Atish Patra <atishp@rivosinc.com> Subject: [PATCH v13 1/7] RISC-V: Clear SIP bit only when using SBI IPI operations Date: Tue, 29 Nov 2022 19:54:43 +0530 [thread overview] Message-ID: <20221129142449.886518-2-apatel@ventanamicro.com> (raw) In-Reply-To: <20221129142449.886518-1-apatel@ventanamicro.com> The software interrupt pending (i.e. [M|S]SIP) bit is writeable for S-mode but read-only for M-mode so we clear this bit only when using SBI IPI operations. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kernel/sbi.c | 8 +++++++- arch/riscv/kernel/smp.c | 2 -- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 5c87db8fdff2..ac99a70ead6a 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -646,8 +646,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target) sbi_send_ipi(target); } +static void sbi_ipi_clear(void) +{ + csr_clear(CSR_IP, IE_SIE); +} + static const struct riscv_ipi_ops sbi_ipi_ops = { - .ipi_inject = sbi_send_cpumask_ipi + .ipi_inject = sbi_send_cpumask_ipi, + .ipi_clear = sbi_ipi_clear }; void __init sbi_init(void) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 760a64518c58..c56d67f53ea9 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -83,8 +83,6 @@ void riscv_clear_ipi(void) { if (ipi_ops && ipi_ops->ipi_clear) ipi_ops->ipi_clear(); - - csr_clear(CSR_IP, IE_SIE); } EXPORT_SYMBOL_GPL(riscv_clear_ipi); -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Atish Patra <atishp@atishpatra.org>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>, Bin Meng <bmeng.cn@gmail.com>, Atish Patra <atishp@rivosinc.com> Subject: [PATCH v13 1/7] RISC-V: Clear SIP bit only when using SBI IPI operations Date: Tue, 29 Nov 2022 19:54:43 +0530 [thread overview] Message-ID: <20221129142449.886518-2-apatel@ventanamicro.com> (raw) In-Reply-To: <20221129142449.886518-1-apatel@ventanamicro.com> The software interrupt pending (i.e. [M|S]SIP) bit is writeable for S-mode but read-only for M-mode so we clear this bit only when using SBI IPI operations. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kernel/sbi.c | 8 +++++++- arch/riscv/kernel/smp.c | 2 -- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 5c87db8fdff2..ac99a70ead6a 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -646,8 +646,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target) sbi_send_ipi(target); } +static void sbi_ipi_clear(void) +{ + csr_clear(CSR_IP, IE_SIE); +} + static const struct riscv_ipi_ops sbi_ipi_ops = { - .ipi_inject = sbi_send_cpumask_ipi + .ipi_inject = sbi_send_cpumask_ipi, + .ipi_clear = sbi_ipi_clear }; void __init sbi_init(void) diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 760a64518c58..c56d67f53ea9 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -83,8 +83,6 @@ void riscv_clear_ipi(void) { if (ipi_ops && ipi_ops->ipi_clear) ipi_ops->ipi_clear(); - - csr_clear(CSR_IP, IE_SIE); } EXPORT_SYMBOL_GPL(riscv_clear_ipi); -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-29 14:25 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-29 14:24 [PATCH v13 0/7] RISC-V IPI Improvements Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-29 14:24 ` Anup Patel [this message] 2022-11-29 14:24 ` [PATCH v13 1/7] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel 2022-11-29 14:24 ` [PATCH v13 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 3/7] genirq: Add mechanism to multiplex a single HW IPI Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-30 14:47 ` Marc Zyngier 2022-11-30 14:47 ` Marc Zyngier 2022-11-30 17:03 ` Anup Patel 2022-11-30 17:03 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 4/7] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-30 16:18 ` Marc Zyngier 2022-11-30 16:18 ` Marc Zyngier 2022-11-30 17:14 ` Anup Patel 2022-11-30 17:14 ` Anup Patel 2022-11-30 18:02 ` Marc Zyngier 2022-11-30 18:02 ` Marc Zyngier 2022-11-30 18:14 ` Anup Patel 2022-11-30 18:14 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 5/7] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 6/7] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 7/7] RISC-V: Use IPIs for remote icache " Anup Patel 2022-11-29 14:24 ` Anup Patel
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