From: Anup Patel <apatel@ventanamicro.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Atish Patra <atishp@atishpatra.org>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>, Atish Patra <atishp@rivosinc.com> Subject: [PATCH v13 7/7] RISC-V: Use IPIs for remote icache flush when possible Date: Tue, 29 Nov 2022 19:54:49 +0530 [thread overview] Message-ID: <20221129142449.886518-8-apatel@ventanamicro.com> (raw) In-Reply-To: <20221129142449.886518-1-apatel@ventanamicro.com> If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote icache flushe directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote icache flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/mm/cacheflush.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 57b40a350420..f10cb47eac3a 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -19,7 +19,7 @@ void flush_icache_all(void) { local_flush_icache_all(); - if (IS_ENABLED(CONFIG_RISCV_SBI)) + if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence()) sbi_remote_fence_i(NULL); else on_each_cpu(ipi_remote_fence_i, NULL, 1); @@ -67,7 +67,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local) * with flush_icache_deferred(). */ smp_mb(); - } else if (IS_ENABLED(CONFIG_RISCV_SBI)) { + } else if (IS_ENABLED(CONFIG_RISCV_SBI) && + !riscv_use_ipi_for_rfence()) { sbi_remote_fence_i(&others); } else { on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1); -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Atish Patra <atishp@atishpatra.org>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>, Atish Patra <atishp@rivosinc.com> Subject: [PATCH v13 7/7] RISC-V: Use IPIs for remote icache flush when possible Date: Tue, 29 Nov 2022 19:54:49 +0530 [thread overview] Message-ID: <20221129142449.886518-8-apatel@ventanamicro.com> (raw) In-Reply-To: <20221129142449.886518-1-apatel@ventanamicro.com> If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote icache flushe directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote icache flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/mm/cacheflush.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 57b40a350420..f10cb47eac3a 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -19,7 +19,7 @@ void flush_icache_all(void) { local_flush_icache_all(); - if (IS_ENABLED(CONFIG_RISCV_SBI)) + if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence()) sbi_remote_fence_i(NULL); else on_each_cpu(ipi_remote_fence_i, NULL, 1); @@ -67,7 +67,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local) * with flush_icache_deferred(). */ smp_mb(); - } else if (IS_ENABLED(CONFIG_RISCV_SBI)) { + } else if (IS_ENABLED(CONFIG_RISCV_SBI) && + !riscv_use_ipi_for_rfence()) { sbi_remote_fence_i(&others); } else { on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1); -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-29 14:26 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-29 14:24 [PATCH v13 0/7] RISC-V IPI Improvements Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 1/7] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 3/7] genirq: Add mechanism to multiplex a single HW IPI Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-30 14:47 ` Marc Zyngier 2022-11-30 14:47 ` Marc Zyngier 2022-11-30 17:03 ` Anup Patel 2022-11-30 17:03 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 4/7] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-30 16:18 ` Marc Zyngier 2022-11-30 16:18 ` Marc Zyngier 2022-11-30 17:14 ` Anup Patel 2022-11-30 17:14 ` Anup Patel 2022-11-30 18:02 ` Marc Zyngier 2022-11-30 18:02 ` Marc Zyngier 2022-11-30 18:14 ` Anup Patel 2022-11-30 18:14 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 5/7] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-29 14:24 ` [PATCH v13 6/7] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel 2022-11-29 14:24 ` Anup Patel 2022-11-29 14:24 ` Anup Patel [this message] 2022-11-29 14:24 ` [PATCH v13 7/7] RISC-V: Use IPIs for remote icache " Anup Patel
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