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From: Andrew Jones <ajones@ventanamicro.com>
To: linux-riscv@lists.infradead.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	Heiko Stuebner <heiko@sntech.de>,
	Anup Patel <apatel@ventanamicro.com>,
	Atish Patra <atishp@rivosinc.com>
Subject: [PATCH v3 3/3] RISC-V: Ensure Zicbom has a valid block size
Date: Tue, 29 Nov 2022 15:34:47 +0100	[thread overview]
Message-ID: <20221129143447.49714-4-ajones@ventanamicro.com> (raw)
In-Reply-To: <20221129143447.49714-1-ajones@ventanamicro.com>

When a DT puts zicbom in the isa string, but does not provide a block
size, ALT_CMO_OP() will attempt to do cache operations on address
zero since the start address will be ANDed with zero. We can't simply
BUG() in riscv_init_cbom_blocksize() when we fail to find a block
size because the failure will happen before logging works, leaving
users to scratch their heads as to why the boot hung. Instead, ensure
Zicbom is disabled and output an error which will hopefully alert
people that the DT needs to be fixed. While at it, add a check that
the block size is a power-of-2 too.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
 arch/riscv/kernel/cpufeature.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 220be7222129..93e45560af30 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -9,6 +9,7 @@
 #include <linux/bitmap.h>
 #include <linux/ctype.h>
 #include <linux/libfdt.h>
+#include <linux/log2.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <asm/alternative.h>
@@ -70,6 +71,18 @@ EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
 
 static bool riscv_isa_extension_check(int id)
 {
+	switch (id) {
+	case RISCV_ISA_EXT_ZICBOM:
+		if (!riscv_cbom_block_size) {
+			pr_err("Zicbom detected in ISA string, but no cbom-block-size found\n");
+			return false;
+		} else if (!is_power_of_2(riscv_cbom_block_size)) {
+			pr_err("cbom-block-size present, but is not a power-of-2\n");
+			return false;
+		}
+		return true;
+	}
+
 	return true;
 }
 
-- 
2.38.1


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  parent reply	other threads:[~2022-11-29 14:35 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-29 14:34 [PATCH v3 0/3] RISC-V: Ensure Zicbom has a valid block size Andrew Jones
2022-11-29 14:34 ` [PATCH v3 1/3] RISC-V: Improve use of isa2hwcap[] Andrew Jones
2022-11-29 14:34 ` [PATCH v3 2/3] RISC-V: Introduce riscv_isa_extension_check Andrew Jones
2022-11-29 14:34 ` Andrew Jones [this message]
2022-11-29 19:45   ` [PATCH v3 3/3] RISC-V: Ensure Zicbom has a valid block size Conor Dooley
2022-11-30  9:46     ` Conor.Dooley
2022-11-30 11:33       ` Andrew Jones
2022-11-30 12:25         ` Andrew Jones
2022-11-30 12:47           ` Conor.Dooley
2022-11-30 13:55             ` Andrew Jones
2022-11-30 14:55               ` Conor.Dooley
2022-12-09 22:18 ` [PATCH v3 0/3] " Palmer Dabbelt
2022-12-09 22:30 ` patchwork-bot+linux-riscv

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