All of lore.kernel.org
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: thuth@redhat.com, iii@linux.ibm.com
Subject: [PATCH v4 12/27] tcg/s390x: Distinguish RRF-a and RRF-c formats
Date: Thu,  8 Dec 2022 20:05:15 -0600	[thread overview]
Message-ID: <20221209020530.396391-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221209020530.396391-1-richard.henderson@linaro.org>

One has 3 register arguments; the other has 2 plus an m3 field.

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target.c.inc | 57 +++++++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 25 deletions(-)

diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 6cf07152a5..d38a602dd9 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -172,18 +172,19 @@ typedef enum S390Opcode {
     RRE_SLBGR   = 0xb989,
     RRE_XGR     = 0xb982,
 
-    RRF_LOCR    = 0xb9f2,
-    RRF_LOCGR   = 0xb9e2,
-    RRF_NRK     = 0xb9f4,
-    RRF_NGRK    = 0xb9e4,
-    RRF_ORK     = 0xb9f6,
-    RRF_OGRK    = 0xb9e6,
-    RRF_SRK     = 0xb9f9,
-    RRF_SGRK    = 0xb9e9,
-    RRF_SLRK    = 0xb9fb,
-    RRF_SLGRK   = 0xb9eb,
-    RRF_XRK     = 0xb9f7,
-    RRF_XGRK    = 0xb9e7,
+    RRFa_NRK    = 0xb9f4,
+    RRFa_NGRK   = 0xb9e4,
+    RRFa_ORK    = 0xb9f6,
+    RRFa_OGRK   = 0xb9e6,
+    RRFa_SRK    = 0xb9f9,
+    RRFa_SGRK   = 0xb9e9,
+    RRFa_SLRK   = 0xb9fb,
+    RRFa_SLGRK  = 0xb9eb,
+    RRFa_XRK    = 0xb9f7,
+    RRFa_XGRK   = 0xb9e7,
+
+    RRFc_LOCR   = 0xb9f2,
+    RRFc_LOCGR  = 0xb9e2,
 
     RR_AR       = 0x1a,
     RR_ALR      = 0x1e,
@@ -538,8 +539,14 @@ static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
     tcg_out32(s, (op << 16) | (r1 << 4) | r2);
 }
 
-static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op,
-                             TCGReg r1, TCGReg r2, int m3)
+static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op,
+                              TCGReg r1, TCGReg r2, TCGReg r3)
+{
+    tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2);
+}
+
+static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op,
+                              TCGReg r1, TCGReg r2, int m3)
 {
     tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
 }
@@ -1324,7 +1331,7 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
     /* Emit: d = 0, t = 1, d = (cc ? t : d).  */
     tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
     tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
-    tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
+    tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc);
 }
 
 static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
@@ -1335,7 +1342,7 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
     if (v3const) {
         tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
     } else {
-        tcg_out_insn(s, RRF, LOCGR, dest, v3, cc);
+        tcg_out_insn(s, RRFc, LOCGR, dest, v3, cc);
     }
 }
 
@@ -1356,7 +1363,7 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
             tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
         }
         /* Emit: if (one bit found) dest = r0.  */
-        tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
+        tcg_out_insn(s, RRFc, LOCGR, dest, TCG_REG_R0, 2);
     }
 }
 
@@ -1960,7 +1967,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         } else if (a0 == a1) {
             tcg_out_insn(s, RR, SR, a0, a2);
         } else {
-            tcg_out_insn(s, RRF, SRK, a0, a1, a2);
+            tcg_out_insn(s, RRFa, SRK, a0, a1, a2);
         }
         break;
 
@@ -1972,7 +1979,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         } else if (a0 == a1) {
             tcg_out_insn(s, RR, NR, a0, a2);
         } else {
-            tcg_out_insn(s, RRF, NRK, a0, a1, a2);
+            tcg_out_insn(s, RRFa, NRK, a0, a1, a2);
         }
         break;
     case INDEX_op_or_i32:
@@ -1983,7 +1990,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         } else if (a0 == a1) {
             tcg_out_insn(s, RR, OR, a0, a2);
         } else {
-            tcg_out_insn(s, RRF, ORK, a0, a1, a2);
+            tcg_out_insn(s, RRFa, ORK, a0, a1, a2);
         }
         break;
     case INDEX_op_xor_i32:
@@ -1994,7 +2001,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         } else if (a0 == a1) {
             tcg_out_insn(s, RR, XR, args[0], args[2]);
         } else {
-            tcg_out_insn(s, RRF, XRK, a0, a1, a2);
+            tcg_out_insn(s, RRFa, XRK, a0, a1, a2);
         }
         break;
 
@@ -2220,7 +2227,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
             a2 = -a2;
             goto do_addi_64;
         } else {
-            tcg_out_insn(s, RRF, SGRK, a0, a1, a2);
+            tcg_out_insn(s, RRFa, SGRK, a0, a1, a2);
         }
         break;
 
@@ -2230,7 +2237,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
             tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
             tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
         } else {
-            tcg_out_insn(s, RRF, NGRK, a0, a1, a2);
+            tcg_out_insn(s, RRFa, NGRK, a0, a1, a2);
         }
         break;
     case INDEX_op_or_i64:
@@ -2239,7 +2246,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
             tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
             tgen_ori(s, TCG_TYPE_I64, a0, a2);
         } else {
-            tcg_out_insn(s, RRF, OGRK, a0, a1, a2);
+            tcg_out_insn(s, RRFa, OGRK, a0, a1, a2);
         }
         break;
     case INDEX_op_xor_i64:
@@ -2248,7 +2255,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
             tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
             tgen_xori(s, TCG_TYPE_I64, a0, a2);
         } else {
-            tcg_out_insn(s, RRF, XGRK, a0, a1, a2);
+            tcg_out_insn(s, RRFa, XGRK, a0, a1, a2);
         }
         break;
 
-- 
2.34.1



  parent reply	other threads:[~2022-12-09  2:17 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-09  2:05 [PATCH v4 00/27] tcg/s390x: misc patches Richard Henderson
2022-12-09  2:05 ` [PATCH v4 01/27] tcg/s390x: Use register pair allocation for div and mulu2 Richard Henderson
2022-12-09  2:05 ` [PATCH v4 02/27] tcg/s390x: Remove TCG_REG_TB Richard Henderson
2022-12-09  2:05 ` [PATCH v4 03/27] tcg/s390x: Always set TCG_TARGET_HAS_direct_jump Richard Henderson
2022-12-12 21:51   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 04/27] tcg/s390x: Remove USE_LONG_BRANCHES Richard Henderson
2022-12-12 21:52   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 05/27] tcg/s390x: Check for long-displacement facility at startup Richard Henderson
2022-12-12 21:54   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 06/27] tcg/s390x: Check for extended-immediate " Richard Henderson
2022-12-12 22:17   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 07/27] tcg/s390x: Check for general-instruction-extension " Richard Henderson
2022-12-12 22:21   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 08/27] tcg/s390x: Check for load-on-condition " Richard Henderson
2022-12-12 22:26   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 09/27] tcg/s390x: Remove FAST_BCR_SER facility check Richard Henderson
2022-12-12 22:08   ` Philippe Mathieu-Daudé
2022-12-09  2:05 ` [PATCH v4 10/27] tcg/s390x: Remove DISTINCT_OPERANDS " Richard Henderson
2022-12-12 22:29   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 11/27] tcg/s390x: Use LARL+AGHI for odd addresses Richard Henderson
2022-12-09  2:05 ` Richard Henderson [this message]
2022-12-09  2:05 ` [PATCH v4 13/27] tcg/s390x: Distinguish RIE formats Richard Henderson
2022-12-09  2:05 ` [PATCH v4 14/27] tcg/s390x: Support MIE2 multiply single instructions Richard Henderson
2022-12-09  2:05 ` [PATCH v4 15/27] tcg/s390x: Support MIE2 MGRK instruction Richard Henderson
2022-12-09  2:05 ` [PATCH v4 16/27] tcg/s390x: Issue XILF directly for xor_i32 Richard Henderson
2022-12-12 22:30   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 17/27] tcg/s390x: Tighten constraints for or_i64 and xor_i64 Richard Henderson
2022-12-12 22:41   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 18/27] tcg/s390x: Tighten constraints for and_i64 Richard Henderson
2022-12-12 22:57   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 19/27] tcg/s390x: Support MIE3 logical operations Richard Henderson
2022-12-09  2:05 ` [PATCH v4 20/27] tcg/s390x: Create tgen_cmp2 to simplify movcond Richard Henderson
2022-12-09  2:05 ` [PATCH v4 21/27] tcg/s390x: Generalize movcond implementation Richard Henderson
2022-12-09  2:05 ` [PATCH v4 22/27] tcg/s390x: Support SELGR instruction in movcond Richard Henderson
2022-12-09  2:05 ` [PATCH v4 23/27] tcg/s390x: Use tgen_movcond_int in tgen_clz Richard Henderson
2022-12-09  2:05 ` [PATCH v4 24/27] tcg/s390x: Implement ctpop operation Richard Henderson
2022-12-09  2:05 ` [PATCH v4 25/27] tcg/s390x: Tighten constraints for 64-bit compare Richard Henderson
2022-12-13 16:25   ` Ilya Leoshkevich
2022-12-13 16:43     ` Richard Henderson
2022-12-13 17:01       ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 26/27] tcg/s390x: Cleanup tcg_out_movi Richard Henderson
2022-12-13 16:29   ` Ilya Leoshkevich
2022-12-09  2:05 ` [PATCH v4 27/27] tcg/s390x: Avoid the constant pool in tcg_out_movi Richard Henderson
2022-12-13 16:31   ` Ilya Leoshkevich
2022-12-13 16:35 ` [PATCH v4 00/27] tcg/s390x: misc patches Ilya Leoshkevich

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221209020530.396391-13-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=iii@linux.ibm.com \
    --cc=qemu-devel@nongnu.org \
    --cc=thuth@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.