From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Subject: [PATCH 01/16] clk: renesas: r9a09g011: Add USB clock and reset entries
Date: Mon, 12 Dec 2022 17:27:49 +0000 [thread overview]
Message-ID: <20221212172804.1277751-2-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20221212172804.1277751-1-biju.das.jz@bp.renesas.com>
Add USB clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a09g011-cpg.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
index b32f82860b2b..40c4c1fd8f07 100644
--- a/drivers/clk/renesas/r9a09g011-cpg.c
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -23,10 +23,12 @@
#define DIV_A DDIV_PACK(0x200, 0, 3)
#define DIV_B DDIV_PACK(0x204, 0, 2)
+#define DIV_D DDIV_PACK(0x204, 4, 2)
#define DIV_E DDIV_PACK(0x204, 8, 1)
#define DIV_W DDIV_PACK(0x328, 0, 3)
#define SEL_B SEL_PLL_PACK(0x214, 0, 1)
+#define SEL_D SEL_PLL_PACK(0x214, 1, 1)
#define SEL_E SEL_PLL_PACK(0x214, 2, 1)
#define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1)
@@ -50,9 +52,11 @@ enum clk_ids {
CLK_PLL4,
CLK_DIV_A,
CLK_DIV_B,
+ CLK_DIV_D,
CLK_DIV_E,
CLK_DIV_W,
CLK_SEL_B,
+ CLK_SEL_D,
CLK_SEL_B_D2,
CLK_SEL_E,
CLK_SEL_W0,
@@ -81,6 +85,13 @@ static const struct clk_div_table dtable_divb[] = {
{0, 0},
};
+static const struct clk_div_table dtable_divd[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {0, 0},
+};
+
static const struct clk_div_table dtable_divw[] = {
{0, 6},
{1, 7},
@@ -94,6 +105,7 @@ static const struct clk_div_table dtable_divw[] = {
/* Mux clock tables */
static const char * const sel_b[] = { ".main", ".divb" };
+static const char * const sel_d[] = { ".main", ".divd" };
static const char * const sel_e[] = { ".main", ".dive" };
static const char * const sel_w[] = { ".main", ".divw" };
@@ -115,10 +127,12 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva),
DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb),
+ DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd),
DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL),
DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw),
DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b),
+ DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d),
DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e),
DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w),
@@ -131,6 +145,9 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
+ DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4),
+ DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5),
+ DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6),
DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12),
DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0),
@@ -169,6 +186,10 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
static const struct rzg2l_reset r9a09g011_resets[] = {
DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
+ DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7),
+ DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8),
+ DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9),
+ DEF_RST(R9A09G011_USB_ARESETN_H, 0x608, 10),
DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1),
--
2.25.1
next prev parent reply other threads:[~2022-12-12 17:28 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-12 17:27 [PATCH 00/16] ADD USB3.1 HOST, Peri and DRD support Biju Das
2022-12-12 17:27 ` Biju Das [this message]
2022-12-21 14:55 ` [PATCH 01/16] clk: renesas: r9a09g011: Add USB clock and reset entries Geert Uytterhoeven
2022-12-12 17:27 ` [PATCH 02/16] dt-bindings: usb: Add RZ/V2M USB3DRD binding Biju Das
2022-12-12 21:17 ` Rob Herring
2022-12-13 6:43 ` Biju Das
2022-12-13 14:29 ` Rob Herring
2022-12-13 15:01 ` Biju Das
2022-12-13 15:54 ` Rob Herring
2023-01-11 14:18 ` Biju Das
2022-12-12 17:27 ` [PATCH 03/16] usb: gadget: Add support for RZ/V2M USB3DRD driver Biju Das
2022-12-12 17:27 ` [PATCH 04/16] dt-bindings: usb: renesas,usb-xhci: Document RZ/V2M support Biju Das
2022-12-16 16:10 ` Rob Herring
2022-12-16 17:10 ` Biju Das
2022-12-12 17:27 ` [PATCH 05/16] usb: host: xhci-plat: Improve clock handling in probe() Biju Das
2022-12-15 10:13 ` Geert Uytterhoeven
2022-12-12 17:27 ` [PATCH 06/16] usb: host: xhci-plat: Add reset support Biju Das
2022-12-15 10:20 ` Geert Uytterhoeven
2022-12-12 17:27 ` [PATCH 07/16] xhci: host: Add Renesas RZ/V2M SoC support Biju Das
2022-12-12 17:27 ` [PATCH 08/16] dt-bindings: usb: renesas,usb3-peri: Update reset property Biju Das
2022-12-12 17:27 ` [PATCH 09/16] dt-bindings: usb: renesas,usb3-peri: Document RZ/V2MA bindings Biju Das
2022-12-12 17:27 ` [PATCH 10/16] usb: gadget: udc: renesas_usb3: Remove drd_reset handling Biju Das
2022-12-12 17:27 ` [PATCH 11/16] usb: gadget: udc: renesas_usb3: Add role switch support for RZ/V2M Biju Das
2022-12-12 17:28 ` [PATCH 13/16] arm64: dts: renesas: r9a09g011: Add USB3 peripheral node Biju Das
2022-12-12 17:28 ` [PATCH 14/16] arm64: dts: renesas: rzv2mevk2: Enable USB3 DRD and Host Biju Das
2022-12-12 17:28 ` [PATCH 15/16] arm64: dts: renesas: rzv2mevk2: Enable USB3 Peripheral Biju Das
2022-12-12 17:28 ` [PATCH 16/16] arm64: dts: renesas: rzv2mevk2: Enable USB3 role switch Biju Das
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