From: Ira Weiny <ira.weiny@intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Steven Rostedt <rostedt@goodmis.org>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-cxl@vger.kernel.org,
Bjorn Helgaas <helgaas@kernel.org>
Subject: [PATCH v5 0/8] cxl: Process event logs
Date: Thu, 05 Jan 2023 15:37:51 -0800 [thread overview]
Message-ID: <20221216-cxl-ev-log-v5-0-180c618ed5d1@intel.com> (raw)
This code has been tested with a newer qemu which allows for more events to be
returned at a time as well an additional QMP event and interrupt injection.
Those patches will follow once they have been cleaned up.
The series is now in 3 parts:
1) Base functionality including interrupts
2) Tracing specific events (Dynamic Capacity Event Record is defered)
3) cxl-test infrastructure for basic tests
To: Dan Williams <dan.j.williams@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Alison Schofield <alison.schofield@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Ben Widawsky <bwidawsk@kernel.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-acpi@vger.kernel.org
Cc: linux-cxl@vger.kernel.org
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes in v5:
- Drop patch 1/9 as it was already picked up in CXL next
- Johnny/Jonathan - base clear event playload length on nr handles
- Minor clean ups
- Link to v4: https://lore.kernel.org/r/20221212070627.1372402-1-ira.weiny@intel.com
---
Davidlohr Bueso (1):
cxl/mem: Wire up event interrupts
Ira Weiny (7):
cxl/mem: Read, trace, and clear events on driver load
cxl/mem: Trace General Media Event Record
cxl/mem: Trace DRAM Event Record
cxl/mem: Trace Memory Module Event Record
cxl/test: Add generic mock events
cxl/test: Add specific events
cxl/test: Simulate event log overflow
drivers/cxl/core/mbox.c | 187 +++++++++++++++++
drivers/cxl/core/trace.h | 479 ++++++++++++++++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 16 ++
drivers/cxl/cxlmem.h | 173 +++++++++++++++
drivers/cxl/cxlpci.h | 6 +
drivers/cxl/pci.c | 237 +++++++++++++++++++++
tools/testing/cxl/test/Kbuild | 2 +-
tools/testing/cxl/test/mem.c | 352 +++++++++++++++++++++++++++++++
8 files changed, 1451 insertions(+), 1 deletion(-)
---
base-commit: 589c3357370a596ef7c99c00baca8ac799fce531
change-id: 20221216-cxl-ev-log-f06383197541
Best regards,
--
Ira Weiny <ira.weiny@intel.com>
next reply other threads:[~2023-01-05 23:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-05 23:37 Ira Weiny [this message]
2023-01-05 23:37 ` [PATCH v5 1/8] cxl/mem: Read, trace, and clear events on driver load Ira Weiny
2023-01-05 23:37 ` [PATCH v5 2/8] cxl/mem: Wire up event interrupts ira.weiny
2023-01-05 23:37 ` [PATCH v5 3/8] cxl/mem: Trace General Media Event Record Ira Weiny
2023-01-05 23:37 ` [PATCH v5 4/8] cxl/mem: Trace DRAM " Ira Weiny
2023-01-05 23:37 ` [PATCH v5 5/8] cxl/mem: Trace Memory Module " Ira Weiny
2023-01-05 23:37 ` [PATCH v5 6/8] cxl/test: Add generic mock events Ira Weiny
2023-01-05 23:37 ` [PATCH v5 7/8] cxl/test: Add specific events Ira Weiny
2023-01-05 23:37 ` [PATCH v5 8/8] cxl/test: Simulate event log overflow Ira Weiny
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