From: Sean Anderson <sean.anderson@seco.com> To: David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, dri-devel@lists.freedesktop.org Cc: Xinwei Kong <kong.kongxinwei@hisilicon.com>, Chen Feng <puck.chen@hisilicon.com>, Tian Tao <tiantao6@hisilicon.com>, Xinliang Liu <xinliang.liu@linaro.org>, linux-kernel@vger.kernel.org, John Stultz <jstultz@google.com>, Sean Anderson <sean.anderson@seco.com> Subject: [PATCH] drm: kirin: Enable COMPILE_TEST Date: Thu, 22 Dec 2022 16:34:26 -0500 [thread overview] Message-ID: <20221222213426.1858941-1-sean.anderson@seco.com> (raw) Use macros for 64-bit operations. This allows compile-testing this driver on 32-bit arches, so enable it. Signed-off-by: Sean Anderson <sean.anderson@seco.com> --- drivers/gpu/drm/hisilicon/kirin/Kconfig | 2 +- drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig index c5265675bf0c..0772f79567ef 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Kconfig +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_HISI_KIRIN tristate "DRM Support for Hisilicon Kirin series SoCs Platform" - depends on DRM && OF && ARM64 + depends on DRM && OF && (ARM64 || COMPILE_TEST) select DRM_KMS_HELPER select DRM_GEM_DMA_HELPER select DRM_MIPI_DSI diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c index d9978b79828c..1cfeffefd4b4 100644 --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -157,8 +157,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps; - m_n_int = temp / (u64)1000000000; - m_n = (temp % (u64)1000000000) / (u64)100000000; + m_n_int = div_u64_rem(temp, 1000000000, &m_n); + m_n /= 100000000; if (m_n_int % 2 == 0) { if (m_n * 6 >= 50) { @@ -229,8 +229,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) phy->pll_fbd_div5f = 1; } - f_kHz = (u64)1000000000 * (u64)m_pll / - ((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll); + f_kHz = div64_u64((u64)1000000000 * (u64)m_pll, + (u64)ref_clk_ps * (u64)n_pll * (u64)q_pll); if (f_kHz >= req_kHz) break; @@ -490,7 +490,7 @@ static void dsi_set_mode_timing(void __iomem *base, hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz; hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz; tmp = (u64)htot * (u64)lane_byte_clk_kHz; - hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz); + hline_time = DIV64_U64_ROUND_UP(tmp, pixel_clk_kHz); /* all specified in byte-lane clocks */ writel(hsa_time, base + VID_HSA_TIME); -- 2.35.1.1320.gc452695387.dirty
WARNING: multiple messages have this Message-ID (diff)
From: Sean Anderson <sean.anderson@seco.com> To: David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, dri-devel@lists.freedesktop.org Cc: Xinliang Liu <xinliang.liu@linaro.org>, Chen Feng <puck.chen@hisilicon.com>, linux-kernel@vger.kernel.org, Sean Anderson <sean.anderson@seco.com>, Xinwei Kong <kong.kongxinwei@hisilicon.com>, John Stultz <jstultz@google.com>, Tian Tao <tiantao6@hisilicon.com> Subject: [PATCH] drm: kirin: Enable COMPILE_TEST Date: Thu, 22 Dec 2022 16:34:26 -0500 [thread overview] Message-ID: <20221222213426.1858941-1-sean.anderson@seco.com> (raw) Use macros for 64-bit operations. This allows compile-testing this driver on 32-bit arches, so enable it. Signed-off-by: Sean Anderson <sean.anderson@seco.com> --- drivers/gpu/drm/hisilicon/kirin/Kconfig | 2 +- drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig index c5265675bf0c..0772f79567ef 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Kconfig +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_HISI_KIRIN tristate "DRM Support for Hisilicon Kirin series SoCs Platform" - depends on DRM && OF && ARM64 + depends on DRM && OF && (ARM64 || COMPILE_TEST) select DRM_KMS_HELPER select DRM_GEM_DMA_HELPER select DRM_MIPI_DSI diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c index d9978b79828c..1cfeffefd4b4 100644 --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -157,8 +157,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps; - m_n_int = temp / (u64)1000000000; - m_n = (temp % (u64)1000000000) / (u64)100000000; + m_n_int = div_u64_rem(temp, 1000000000, &m_n); + m_n /= 100000000; if (m_n_int % 2 == 0) { if (m_n * 6 >= 50) { @@ -229,8 +229,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) phy->pll_fbd_div5f = 1; } - f_kHz = (u64)1000000000 * (u64)m_pll / - ((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll); + f_kHz = div64_u64((u64)1000000000 * (u64)m_pll, + (u64)ref_clk_ps * (u64)n_pll * (u64)q_pll); if (f_kHz >= req_kHz) break; @@ -490,7 +490,7 @@ static void dsi_set_mode_timing(void __iomem *base, hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz; hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz; tmp = (u64)htot * (u64)lane_byte_clk_kHz; - hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz); + hline_time = DIV64_U64_ROUND_UP(tmp, pixel_clk_kHz); /* all specified in byte-lane clocks */ writel(hsa_time, base + VID_HSA_TIME); -- 2.35.1.1320.gc452695387.dirty
next reply other threads:[~2022-12-22 21:34 UTC|newest] Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-22 21:34 Sean Anderson [this message] 2022-12-22 21:34 ` [PATCH] drm: kirin: Enable COMPILE_TEST Sean Anderson 2022-12-24 10:02 ` kernel test robot 2022-12-24 10:02 ` kernel test robot
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