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From: Irui Wang <irui.wang@mediatek.com>
To: Hans Verkuil <hverkuil-cisco@xs4all.nl>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	<angelogioacchino.delregno@collabora.com>,
	<nicolas.dufresne@collabora.com>,
	kyrie wu <kyrie.wu@mediatek.com>
Cc: <Project_Global_Chrome_Upstream_Group@mediatek.com>,
	<devicetree@vger.kernel.org>, <linux-media@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	Tomasz Figa <tfiga@chromium.org>, <xia.jiang@mediatek.com>,
	<maoguang.meng@mediatek.com>, Irui Wang <irui.wang@mediatek.com>
Subject: [V1,2/2] arm64: dts: mt8195: add jpeg decode device node
Date: Thu, 12 Jan 2023 16:45:03 +0800	[thread overview]
Message-ID: <20230112084503.4277-3-irui.wang@mediatek.com> (raw)
In-Reply-To: <20230112084503.4277-1-irui.wang@mediatek.com>

From: kyrie wu <kyrie.wu@mediatek.com>

add mt8195 jpegdec device node

Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
Signed-off-by: irui wang <irui.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 60 ++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index af49ec352bfe..d5d0aeac57e4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2192,6 +2192,66 @@
 			};
 		};
 
+		jpgdec-master {
+			compatible = "mediatek,mt8195-jpgdec";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+			iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			jpgdec@1a040000 {
+				compatible = "mediatek,mt8195-jpgdec-hw";
+				reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
+				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys CLK_VENC_JPGDEC>;
+				clock-names = "jpgdec";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+			};
+
+			jpgdec@1a050000 {
+				compatible = "mediatek,mt8195-jpgdec-hw";
+				reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
+				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
+				clock-names = "jpgdec";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+			};
+
+			jpgdec@1b040000 {
+				compatible = "mediatek,mt8195-jpgdec-hw";
+				reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
+				iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
+				interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
+				clock-names = "jpgdec";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb20: larb@1b010000 {
 			compatible = "mediatek,mt8195-smi-larb";
 			reg = <0 0x1b010000 0 0x1000>;
-- 
2.18.0


WARNING: multiple messages have this Message-ID (diff)
From: Irui Wang <irui.wang@mediatek.com>
To: Hans Verkuil <hverkuil-cisco@xs4all.nl>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	<angelogioacchino.delregno@collabora.com>,
	<nicolas.dufresne@collabora.com>,
	kyrie wu <kyrie.wu@mediatek.com>
Cc: <Project_Global_Chrome_Upstream_Group@mediatek.com>,
	<devicetree@vger.kernel.org>, <linux-media@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	Tomasz Figa <tfiga@chromium.org>, <xia.jiang@mediatek.com>,
	<maoguang.meng@mediatek.com>, Irui Wang <irui.wang@mediatek.com>
Subject: [V1,2/2] arm64: dts: mt8195: add jpeg decode device node
Date: Thu, 12 Jan 2023 16:45:03 +0800	[thread overview]
Message-ID: <20230112084503.4277-3-irui.wang@mediatek.com> (raw)
In-Reply-To: <20230112084503.4277-1-irui.wang@mediatek.com>

From: kyrie wu <kyrie.wu@mediatek.com>

add mt8195 jpegdec device node

Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
Signed-off-by: irui wang <irui.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 60 ++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index af49ec352bfe..d5d0aeac57e4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2192,6 +2192,66 @@
 			};
 		};
 
+		jpgdec-master {
+			compatible = "mediatek,mt8195-jpgdec";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+			iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			jpgdec@1a040000 {
+				compatible = "mediatek,mt8195-jpgdec-hw";
+				reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
+				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys CLK_VENC_JPGDEC>;
+				clock-names = "jpgdec";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+			};
+
+			jpgdec@1a050000 {
+				compatible = "mediatek,mt8195-jpgdec-hw";
+				reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
+				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
+				clock-names = "jpgdec";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+			};
+
+			jpgdec@1b040000 {
+				compatible = "mediatek,mt8195-jpgdec-hw";
+				reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
+				iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
+				interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
+				clock-names = "jpgdec";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb20: larb@1b010000 {
 			compatible = "mediatek,mt8195-smi-larb";
 			reg = <0 0x1b010000 0 0x1000>;
-- 
2.18.0


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  parent reply	other threads:[~2023-01-12  8:47 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-12  8:45 [V1,0/2] Add jpeg enc & dec device node for MT8195 Irui Wang
2023-01-12  8:45 ` Irui Wang
2023-01-12  8:45 ` [V1,1/2] arm64: dts: mt8195: add jpeg encode device node Irui Wang
2023-01-12  8:45   ` Irui Wang
2023-01-12  8:45 ` Irui Wang [this message]
2023-01-12  8:45   ` [V1,2/2] arm64: dts: mt8195: add jpeg decode " Irui Wang
2023-01-25 15:22 ` [V1,0/2] Add jpeg enc & dec device node for MT8195 Matthias Brugger
2023-01-25 15:22   ` Matthias Brugger

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