All of lore.kernel.org
 help / color / mirror / Atom feed
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, bp@alien8.de,
	tony.luck@intel.com
Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	james.morse@arm.com, mchehab@kernel.org, rric@kernel.org,
	linux-edac@vger.kernel.org, quic_ppareek@quicinc.com,
	luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v6 04/17] dt-bindings: arm: msm: Update the maintainers for LLCC
Date: Wed, 18 Jan 2023 20:38:51 +0530	[thread overview]
Message-ID: <20230118150904.26913-5-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org>

Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him
maintaining with a new identity. So his entry needs to be removed.

Also, Sai Prakash Ranjan's email address should be updated to use
quicinc domain.

Cc: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Acked-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
index 38efcad56dbd..d1df49ffcc1b 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Last Level Cache Controller
 
 maintainers:
-  - Rishabh Bhatnagar <rishabhb@codeaurora.org>
-  - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
+  - Sai Prakash Ranjan <quic_saipraka@quicinc.com>
 
 description: |
   LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
-- 
2.25.1


  parent reply	other threads:[~2023-01-18 15:09 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-18 15:08 [PATCH v6 00/17] Qcom: LLCC/EDAC: Fix base address used for LLCC banks Manivannan Sadhasivam
2023-01-18 15:08 ` [PATCH v6 01/17] EDAC/device: Respect any driver-supplied workqueue polling value Manivannan Sadhasivam
2023-01-18 17:46   ` Bjorn Andersson
2023-01-18 19:05     ` Borislav Petkov
2023-01-19 10:55   ` Borislav Petkov
2023-01-18 15:08 ` [PATCH v6 02/17] EDAC/qcom: Add platform_device_id table for module autoloading Manivannan Sadhasivam
2023-01-20 16:10   ` Borislav Petkov
2023-01-18 15:08 ` [PATCH v6 03/17] EDAC/qcom: Do not pass llcc_driv_data as edac_device_ctl_info's pvt_info Manivannan Sadhasivam
2023-01-20 18:56   ` Borislav Petkov
2023-01-18 15:08 ` Manivannan Sadhasivam [this message]
2023-01-18 15:08 ` [PATCH v6 05/17] dt-bindings: arm: msm: Fix register regions used for LLCC banks Manivannan Sadhasivam
2023-01-18 15:08 ` [PATCH v6 06/17] arm64: dts: qcom: sdm845: Fix the base addresses of " Manivannan Sadhasivam
2023-01-18 15:08 ` [PATCH v6 07/17] arm64: dts: qcom: sc7180: " Manivannan Sadhasivam
2023-01-18 15:08 ` [PATCH v6 08/17] arm64: dts: qcom: sc7280: " Manivannan Sadhasivam
2023-01-18 15:08 ` [PATCH v6 09/17] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2023-01-18 15:08 ` [PATCH v6 10/17] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
2023-01-18 15:08 ` [PATCH v6 11/17] arm64: dts: qcom: sm8250: " Manivannan Sadhasivam
2023-01-18 15:08 ` [PATCH v6 12/17] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
2023-01-18 15:09 ` [PATCH v6 13/17] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
2023-01-18 15:09 ` [PATCH v6 14/17] arm64: dts: qcom: sm6350: " Manivannan Sadhasivam
2023-01-18 15:09 ` [PATCH v6 15/17] qcom: llcc/edac: Fix the base address used for accessing " Manivannan Sadhasivam
2023-01-18 15:09 ` [PATCH v6 16/17] qcom: llcc/edac: Support polling mode for ECC handling Manivannan Sadhasivam
2023-01-20 19:04   ` Borislav Petkov
2023-01-18 15:09 ` [PATCH v6 17/17] soc: qcom: llcc: Do not create EDAC platform device on SDM845 Manivannan Sadhasivam
2023-01-18 15:37   ` Krzysztof Kozlowski
2023-01-18 15:59     ` Manivannan Sadhasivam
2023-01-18 16:05       ` Krzysztof Kozlowski
2023-01-18 16:26         ` Manivannan Sadhasivam
2023-01-18 17:06           ` Krzysztof Kozlowski

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230118150904.26913-5-manivannan.sadhasivam@linaro.org \
    --to=manivannan.sadhasivam@linaro.org \
    --cc=ahalaney@redhat.com \
    --cc=andersson@kernel.org \
    --cc=bp@alien8.de \
    --cc=james.morse@arm.com \
    --cc=konrad.dybcio@linaro.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=krzysztof.kozlowski@linaro.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-edac@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=luca.weiss@fairphone.com \
    --cc=mchehab@kernel.org \
    --cc=quic_ppareek@quicinc.com \
    --cc=quic_saipraka@quicinc.com \
    --cc=robh+dt@kernel.org \
    --cc=rric@kernel.org \
    --cc=steev@kali.org \
    --cc=tony.luck@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.