From: Brad Larson <brad@pensando.io> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 10/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Wed, 18 Jan 2023 19:39:13 -0800 [thread overview] Message-ID: <20230119033918.44117-11-blarson@amd.com> (raw) In-Reply-To: <20230119033918.44117-1-blarson@amd.com> The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson <blarson@amd.com> --- Changes since v6: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 676313e1bdad..e042781d3db5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -89,6 +90,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -978,6 +980,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1700,6 +1709,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1825,6 +1836,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1850,6 +1865,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Brad Larson <brad@pensando.io> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-spi@vger.kernel.org, adrian.hunter@intel.com, alcooperx@gmail.com, andy.shevchenko@gmail.com, arnd@arndb.de, brad@pensando.io, blarson@amd.com, brendan.higgins@linux.dev, briannorris@chromium.org, brijeshkumar.singh@amd.com, catalin.marinas@arm.com, davidgow@google.com, gsomlo@gmail.com, gerg@linux-m68k.org, krzk@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, lee.jones@linaro.org, broonie@kernel.org, yamada.masahiro@socionext.com, p.zabel@pengutronix.de, piotrs@cadence.com, p.yadav@ti.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, fancer.lancer@gmail.com, skhan@linuxfoundation.org, suravee.suthikulpanit@amd.com, thomas.lendacky@amd.com, tonyhuang.sunplus@gmail.com, ulf.hansson@linaro.org, vaishnav.a@ti.com, will@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v9 10/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Wed, 18 Jan 2023 19:39:13 -0800 [thread overview] Message-ID: <20230119033918.44117-11-blarson@amd.com> (raw) In-Reply-To: <20230119033918.44117-1-blarson@amd.com> The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson <blarson@amd.com> --- Changes since v6: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 676313e1bdad..e042781d3db5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -89,6 +90,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -978,6 +980,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1700,6 +1709,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1825,6 +1836,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1850,6 +1865,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } }; -- 2.17.1
next prev parent reply other threads:[~2023-01-19 3:44 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-19 3:39 [PATCH v9 00/15] Support AMD Pensando Elba SoC Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 01/15] dt-bindings: arm: add AMD Pensando boards Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 02/15] dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 03/15] dt-bindings: spi: cdns: Add compatible for " Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller bindings Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 05/15] dt-bindings: mfd: syscon: Add amd,pensando-elba-syscon compatible Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 06/15] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando System Resource chip Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 07/15] MAINTAINERS: Add entry for AMD PENSANDO Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 08/15] arm64: Add config for AMD Pensando SoC platforms Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 09/15] arm64: dts: Add AMD Pensando Elba SoC support Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` Brad Larson [this message] 2023-01-19 3:39 ` [PATCH v9 10/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Brad Larson 2023-01-19 3:39 ` [PATCH v9 11/15] spi: dw: Add support " Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 12/15] mmc: sdhci-cadence: Enable device specific override of writel() Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 14/15] mmc: sdhci-cadence: Support mmc hardware reset Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 8:57 ` Arnd Bergmann 2023-01-19 8:57 ` Arnd Bergmann 2023-02-07 1:51 ` Brad Larson 2023-02-07 1:51 ` Brad Larson 2023-01-19 3:39 ` [PATCH v9 15/15] spi: pensando-sr: Add AMD Pensando SoC System Resource Brad Larson 2023-01-19 3:39 ` Brad Larson 2023-01-19 9:22 ` Arnd Bergmann 2023-01-19 9:22 ` Arnd Bergmann 2023-01-19 3:51 [PATCH v9 00/15] Support AMD Pensando Elba SoC Brad Larson 2023-01-19 3:51 ` [PATCH v9 10/15] spi: cadence-quadspi: Add compatible for " Brad Larson 2023-01-19 3:51 ` Brad Larson
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