From: Achal Verma <a-verma1@ti.com> To: <mranostay@ti.com>, <rogerq@kernel.org>, <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>, <krzysztof.kozlowski@linaro.org>, <vigneshr@ti.com>, <tjoseph@cadence.com>, <sergio.paracuellos@gmail.com>, <pthombar@cadence.com>, <linux-pci@vger.kernel.org> Cc: <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-omap@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v9 5/5] PCI: j721e: add j784s4 PCIe configuration Date: Sun, 22 Jan 2023 17:51:21 +0530 [thread overview] Message-ID: <20230122122121.3552375-6-a-verma1@ti.com> (raw) In-Reply-To: <20230122122121.3552375-1-a-verma1@ti.com> From: Matt Ranostay <mranostay@ti.com> Add PCIe configuration for j784s4 platform which has 4x lane support. Tested-by: Achal Verma <a-verma1@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Achal Verma <a-verma1@ti.com> --- drivers/pci/controller/cadence/pci-j721e.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 58dcac9021e4..cce7b391f931 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = { .max_lanes = 1, }; +static const struct j721e_pcie_data j784s4_pcie_rc_data = { + .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, + .byte_access_allowed = false, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + +static const struct j721e_pcie_data j784s4_pcie_ep_data = { + .mode = PCI_MODE_EP, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + static const struct of_device_id of_j721e_pcie_match[] = { { .compatible = "ti,j721e-pcie-host", @@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,am64-pcie-ep", .data = &am64_pcie_ep_data, }, + { + .compatible = "ti,j784s4-pcie-host", + .data = &j784s4_pcie_rc_data, + }, + { + .compatible = "ti,j784s4-pcie-ep", + .data = &j784s4_pcie_ep_data, + }, {}, }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Achal Verma <a-verma1@ti.com> To: <mranostay@ti.com>, <rogerq@kernel.org>, <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>, <krzysztof.kozlowski@linaro.org>, <vigneshr@ti.com>, <tjoseph@cadence.com>, <sergio.paracuellos@gmail.com>, <pthombar@cadence.com>, <linux-pci@vger.kernel.org> Cc: <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-omap@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v9 5/5] PCI: j721e: add j784s4 PCIe configuration Date: Sun, 22 Jan 2023 17:51:21 +0530 [thread overview] Message-ID: <20230122122121.3552375-6-a-verma1@ti.com> (raw) In-Reply-To: <20230122122121.3552375-1-a-verma1@ti.com> From: Matt Ranostay <mranostay@ti.com> Add PCIe configuration for j784s4 platform which has 4x lane support. Tested-by: Achal Verma <a-verma1@ti.com> Signed-off-by: Matt Ranostay <mranostay@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Achal Verma <a-verma1@ti.com> --- drivers/pci/controller/cadence/pci-j721e.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 58dcac9021e4..cce7b391f931 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = { .max_lanes = 1, }; +static const struct j721e_pcie_data j784s4_pcie_rc_data = { + .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, + .byte_access_allowed = false, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + +static const struct j721e_pcie_data j784s4_pcie_ep_data = { + .mode = PCI_MODE_EP, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + static const struct of_device_id of_j721e_pcie_match[] = { { .compatible = "ti,j721e-pcie-host", @@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,am64-pcie-ep", .data = &am64_pcie_ep_data, }, + { + .compatible = "ti,j784s4-pcie-host", + .data = &j784s4_pcie_rc_data, + }, + { + .compatible = "ti,j784s4-pcie-ep", + .data = &j784s4_pcie_ep_data, + }, {}, }; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-01-22 12:22 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-22 12:21 [PATCH v9 0/5] PCI: add 4x lane support for pci-j721e controllers Achal Verma 2023-01-22 12:21 ` Achal Verma 2023-01-22 12:21 ` [PATCH v9 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Achal Verma 2023-01-22 12:21 ` Achal Verma 2023-01-22 14:30 ` Krzysztof Kozlowski 2023-01-22 14:30 ` Krzysztof Kozlowski 2023-01-22 12:21 ` [PATCH v9 2/5] PCI: j721e: Add per platform maximum lane settings Achal Verma 2023-01-22 12:21 ` Achal Verma 2023-01-22 12:21 ` [PATCH v9 3/5] PCI: j721e: Add PCIe 4x lane selection support Achal Verma 2023-01-22 12:21 ` Achal Verma 2023-01-22 12:21 ` [PATCH v9 4/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Achal Verma 2023-01-22 12:21 ` Achal Verma 2023-01-22 12:21 ` Achal Verma [this message] 2023-01-22 12:21 ` [PATCH v9 5/5] PCI: j721e: add j784s4 PCIe configuration Achal Verma
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