From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
To: alberto.dassatti@heig-vd.ch
Cc: xxm@rock-chips.com, wenrui.li@rock-chips.com,
rick.wertenbroek@heig-vd.ch,
"Rick Wertenbroek" <rick.wertenbroek@gmail.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Jani Nikula" <jani.nikula@intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Mikko Kovanen" <mikko.kovanen@aavamobile.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH 7/8] PCI: rockchip: Fixed legacy IRQ generation for endpoint
Date: Thu, 26 Jan 2023 14:50:47 +0100 [thread overview]
Message-ID: <20230126135049.708524-8-rick.wertenbroek@gmail.com> (raw)
In-Reply-To: <20230126135049.708524-1-rick.wertenbroek@gmail.com>
Added generation of legacy IRQ (INTx) for the RK3399 SoC PCIe EP core.
The generation of the legacy interrupt was validated with the PCIe EP
test driver. Generation of IRQ through the core is documented in the
TRM and is done through the PCIE_CLIENT_LEGACY_INT_CTRL register of
the core.
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
---
drivers/pci/controller/pcie-rockchip-ep.c | 32 ++++++-----------------
drivers/pci/controller/pcie-rockchip.h | 6 +++++
2 files changed, 14 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index a682a941d..a58c9d56b 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -333,15 +333,6 @@ static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
u32 status;
u8 msg_code;
- if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR ||
- ep->irq_pci_fn != fn)) {
- rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
- AXI_WRAPPER_NOR_MSG,
- ep->irq_phys_addr, 0, 0);
- ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR;
- ep->irq_pci_fn = fn;
- }
-
intx &= 3;
if (is_asserted) {
ep->irq_pending |= BIT(intx);
@@ -351,22 +342,15 @@ static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx;
}
- status = rockchip_pcie_read(rockchip,
- ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
- ROCKCHIP_PCIE_EP_CMD_STATUS);
- status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
-
- if ((status != 0) ^ (ep->irq_pending != 0)) {
- status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
- rockchip_pcie_write(rockchip, status,
- ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
- ROCKCHIP_PCIE_EP_CMD_STATUS);
+ if (is_asserted) {
+ rockchip_pcie_write(&ep->rockchip,
+ PCIE_CLIENT_INT_IN_ASSERT | PCIE_CLIENT_INT_PEND_ST_PEND,
+ PCIE_CLIENT_LEGACY_INT_CTRL);
+ } else {
+ rockchip_pcie_write(&ep->rockchip,
+ PCIE_CLIENT_INT_IN_DEASSERT | PCIE_CLIENT_INT_PEND_ST_NORMAL,
+ PCIE_CLIENT_LEGACY_INT_CTRL);
}
-
- offset =
- ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) |
- ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA;
- writel(0, ep->irq_cpu_addr + offset);
}
static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index 72e427a0f..e90c2a2b8 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -39,6 +39,12 @@
#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20)
+#define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c)
+#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002)
+#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0)
+#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001)
+#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0)
+#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20)
#define PCIE_CLIENT_PHY_ST BIT(12)
#define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c)
#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
To: alberto.dassatti@heig-vd.ch
Cc: xxm@rock-chips.com, wenrui.li@rock-chips.com,
rick.wertenbroek@heig-vd.ch,
"Rick Wertenbroek" <rick.wertenbroek@gmail.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Jani Nikula" <jani.nikula@intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Mikko Kovanen" <mikko.kovanen@aavamobile.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH 7/8] PCI: rockchip: Fixed legacy IRQ generation for endpoint
Date: Thu, 26 Jan 2023 14:50:47 +0100 [thread overview]
Message-ID: <20230126135049.708524-8-rick.wertenbroek@gmail.com> (raw)
In-Reply-To: <20230126135049.708524-1-rick.wertenbroek@gmail.com>
Added generation of legacy IRQ (INTx) for the RK3399 SoC PCIe EP core.
The generation of the legacy interrupt was validated with the PCIe EP
test driver. Generation of IRQ through the core is documented in the
TRM and is done through the PCIE_CLIENT_LEGACY_INT_CTRL register of
the core.
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
---
drivers/pci/controller/pcie-rockchip-ep.c | 32 ++++++-----------------
drivers/pci/controller/pcie-rockchip.h | 6 +++++
2 files changed, 14 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index a682a941d..a58c9d56b 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -333,15 +333,6 @@ static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
u32 status;
u8 msg_code;
- if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR ||
- ep->irq_pci_fn != fn)) {
- rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
- AXI_WRAPPER_NOR_MSG,
- ep->irq_phys_addr, 0, 0);
- ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR;
- ep->irq_pci_fn = fn;
- }
-
intx &= 3;
if (is_asserted) {
ep->irq_pending |= BIT(intx);
@@ -351,22 +342,15 @@ static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx;
}
- status = rockchip_pcie_read(rockchip,
- ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
- ROCKCHIP_PCIE_EP_CMD_STATUS);
- status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
-
- if ((status != 0) ^ (ep->irq_pending != 0)) {
- status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
- rockchip_pcie_write(rockchip, status,
- ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
- ROCKCHIP_PCIE_EP_CMD_STATUS);
+ if (is_asserted) {
+ rockchip_pcie_write(&ep->rockchip,
+ PCIE_CLIENT_INT_IN_ASSERT | PCIE_CLIENT_INT_PEND_ST_PEND,
+ PCIE_CLIENT_LEGACY_INT_CTRL);
+ } else {
+ rockchip_pcie_write(&ep->rockchip,
+ PCIE_CLIENT_INT_IN_DEASSERT | PCIE_CLIENT_INT_PEND_ST_NORMAL,
+ PCIE_CLIENT_LEGACY_INT_CTRL);
}
-
- offset =
- ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) |
- ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA;
- writel(0, ep->irq_cpu_addr + offset);
}
static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index 72e427a0f..e90c2a2b8 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -39,6 +39,12 @@
#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20)
+#define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c)
+#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002)
+#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0)
+#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001)
+#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0)
+#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20)
#define PCIE_CLIENT_PHY_ST BIT(12)
#define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c)
#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
To: alberto.dassatti@heig-vd.ch
Cc: xxm@rock-chips.com, wenrui.li@rock-chips.com,
rick.wertenbroek@heig-vd.ch,
"Rick Wertenbroek" <rick.wertenbroek@gmail.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Jani Nikula" <jani.nikula@intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Mikko Kovanen" <mikko.kovanen@aavamobile.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH 7/8] PCI: rockchip: Fixed legacy IRQ generation for endpoint
Date: Thu, 26 Jan 2023 14:50:47 +0100 [thread overview]
Message-ID: <20230126135049.708524-8-rick.wertenbroek@gmail.com> (raw)
In-Reply-To: <20230126135049.708524-1-rick.wertenbroek@gmail.com>
Added generation of legacy IRQ (INTx) for the RK3399 SoC PCIe EP core.
The generation of the legacy interrupt was validated with the PCIe EP
test driver. Generation of IRQ through the core is documented in the
TRM and is done through the PCIE_CLIENT_LEGACY_INT_CTRL register of
the core.
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
---
drivers/pci/controller/pcie-rockchip-ep.c | 32 ++++++-----------------
drivers/pci/controller/pcie-rockchip.h | 6 +++++
2 files changed, 14 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index a682a941d..a58c9d56b 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -333,15 +333,6 @@ static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
u32 status;
u8 msg_code;
- if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR ||
- ep->irq_pci_fn != fn)) {
- rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
- AXI_WRAPPER_NOR_MSG,
- ep->irq_phys_addr, 0, 0);
- ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR;
- ep->irq_pci_fn = fn;
- }
-
intx &= 3;
if (is_asserted) {
ep->irq_pending |= BIT(intx);
@@ -351,22 +342,15 @@ static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx;
}
- status = rockchip_pcie_read(rockchip,
- ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
- ROCKCHIP_PCIE_EP_CMD_STATUS);
- status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
-
- if ((status != 0) ^ (ep->irq_pending != 0)) {
- status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
- rockchip_pcie_write(rockchip, status,
- ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
- ROCKCHIP_PCIE_EP_CMD_STATUS);
+ if (is_asserted) {
+ rockchip_pcie_write(&ep->rockchip,
+ PCIE_CLIENT_INT_IN_ASSERT | PCIE_CLIENT_INT_PEND_ST_PEND,
+ PCIE_CLIENT_LEGACY_INT_CTRL);
+ } else {
+ rockchip_pcie_write(&ep->rockchip,
+ PCIE_CLIENT_INT_IN_DEASSERT | PCIE_CLIENT_INT_PEND_ST_NORMAL,
+ PCIE_CLIENT_LEGACY_INT_CTRL);
}
-
- offset =
- ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) |
- ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA;
- writel(0, ep->irq_cpu_addr + offset);
}
static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
index 72e427a0f..e90c2a2b8 100644
--- a/drivers/pci/controller/pcie-rockchip.h
+++ b/drivers/pci/controller/pcie-rockchip.h
@@ -39,6 +39,12 @@
#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20)
+#define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c)
+#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002)
+#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0)
+#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001)
+#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0)
+#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20)
#define PCIE_CLIENT_PHY_ST BIT(12)
#define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c)
#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-01-26 13:53 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-26 13:50 [PATCH 0/8] PCI: rockchip: Fix PCIe endpoint controller driver Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` [PATCH 1/8] PCI: rockchip: Removed writes to unused registers Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` [PATCH 2/8] PCI: rockchip: Fixed setup of Device ID Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` [PATCH 3/8] PCI: rockchip: Fixed endpoint controller Configuration Request Retry Status Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` [PATCH 4/8] PCI: rockchip: Added poll and timeout to wait for PHY PLLs to be locked Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 14:42 ` Bjorn Helgaas
2023-01-26 14:42 ` Bjorn Helgaas
2023-01-26 14:42 ` Bjorn Helgaas
2023-01-26 13:50 ` [PATCH 5/8] PCI: rockchip: Added dtsi entry for PCIe endpoint controller Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 15:23 ` Krzysztof Kozlowski
2023-01-26 15:23 ` Krzysztof Kozlowski
2023-01-26 15:23 ` Krzysztof Kozlowski
2023-01-26 15:30 ` Rick Wertenbroek
2023-01-26 15:30 ` Rick Wertenbroek
2023-01-26 15:30 ` Rick Wertenbroek
2023-01-26 15:43 ` Krzysztof Kozlowski
2023-01-26 15:43 ` Krzysztof Kozlowski
2023-01-26 15:43 ` Krzysztof Kozlowski
2023-01-27 8:42 ` ALOK TIWARI
2023-01-27 8:42 ` ALOK TIWARI
2023-01-27 8:42 ` ALOK TIWARI
2023-01-30 13:52 ` Rick Wertenbroek
2023-01-30 13:52 ` Rick Wertenbroek
2023-01-30 13:52 ` Rick Wertenbroek
2023-01-30 15:04 ` Rob Herring
2023-01-30 15:04 ` Rob Herring
2023-01-30 15:04 ` Rob Herring
2023-01-26 13:50 ` [PATCH 6/8] PCI: rockchip: Fixed window mapping and address translation for endpoint Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek [this message]
2023-01-26 13:50 ` [PATCH 7/8] PCI: rockchip: Fixed legacy IRQ generation " Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 15:25 ` Krzysztof Kozlowski
2023-01-26 15:25 ` Krzysztof Kozlowski
2023-01-26 15:25 ` Krzysztof Kozlowski
2023-01-28 9:19 ` kernel test robot
2023-01-28 9:19 ` kernel test robot
2023-01-28 9:19 ` kernel test robot
2023-01-26 13:50 ` [PATCH 8/8] PCI: rockchip: Fixed MSI generation from PCIe endpoint core Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 13:50 ` Rick Wertenbroek
2023-01-26 15:26 ` Krzysztof Kozlowski
2023-01-26 15:26 ` Krzysztof Kozlowski
2023-01-26 15:26 ` Krzysztof Kozlowski
2023-01-26 14:52 ` [PATCH 0/8] PCI: rockchip: Fix PCIe endpoint controller driver Bjorn Helgaas
2023-01-26 14:52 ` Bjorn Helgaas
2023-01-26 14:52 ` Bjorn Helgaas
2023-01-26 15:23 ` Rick Wertenbroek
2023-01-26 15:23 ` Rick Wertenbroek
2023-01-26 15:23 ` Rick Wertenbroek
2023-01-26 15:49 ` Bjorn Helgaas
2023-01-26 15:49 ` Bjorn Helgaas
2023-01-26 15:49 ` Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230126135049.708524-8-rick.wertenbroek@gmail.com \
--to=rick.wertenbroek@gmail.com \
--cc=alberto.dassatti@heig-vd.ch \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=heiko@sntech.de \
--cc=jani.nikula@intel.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=mikko.kovanen@aavamobile.com \
--cc=rick.wertenbroek@heig-vd.ch \
--cc=robh+dt@kernel.org \
--cc=rodrigo.vivi@intel.com \
--cc=shawn.lin@rock-chips.com \
--cc=wenrui.li@rock-chips.com \
--cc=xxm@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.