From: Marcel Ziswiler <marcel@ziswiler.com> To: devicetree@vger.kernel.org Cc: Liu Ying <victor.liu@nxp.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, linux-imx@nxp.com, Joakim Zhang <qiangqing.zhang@nxp.com>, Marcel Ziswiler <marcel.ziswiler@toradex.com>, Alexander Stein <alexander.stein@ew.tq-group.com>, Fabio Estevam <festevam@gmail.com>, Frank Li <Frank.Li@nxp.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Max Krummenacher <max.krummenacher@toradex.com>, Peng Fan <peng.fan@nxp.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, Philippe Schenker <philippe.schenker@toradex.com>, Rob Herring <robh+dt@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Shawn Guo <shawnguo@kernel.org> Subject: [PATCH v6 05/10] arm64: dts: imx8qxp: add flexcan in adma Date: Thu, 2 Feb 2023 16:32:15 +0100 [thread overview] Message-ID: <20230202153221.197308-6-marcel@ziswiler.com> (raw) In-Reply-To: <20230202153221.197308-1-marcel@ziswiler.com> From: Joakim Zhang <qiangqing.zhang@nxp.com> Add FlexCAN decive in adma subsystem. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # TQMa8XQP --- Changes in v6: - Add Alexander's tested-by. Thanks! Changes in v4: - New patch combining the following downstream patches: commit e8fe3f57223a ("arm64: dts: imx8qxp: add FlexCAN in adma") commit 4e90361f1ed3 ("arm64: dts: imx8qxp: add multi-pd support for CAN1/2") commit 899f516e61f8 ("arm64: dts: imx8: dma: fully switched to new clk binding") commit 8a28ca15a058 ("arm64: dts: imx8qxp: drop multi-pd for CAN device") commit c493402197dd ("arm64: dts: imx8: update CAN fsl,clk-source and fsl,scu-index property") .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 6ccf926b77a5..2dce8f2ee3ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -298,6 +298,65 @@ adc1: adc@5a890000 { status = "disabled"; }; + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8d0000 0x10000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_0>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8e0000 0x10000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_1>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <1>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8f0000 0x10000>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_2>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <2>; + status = "disabled"; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; @@ -369,4 +428,17 @@ adc1_lpcg: clock-controller@5ac90000 { "adc1_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_ADC_1>; }; + + can0_lpcg: clock-controller@5acd0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acd0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; + clock-output-names = "can0_lpcg_pe_clk", + "can0_lpcg_ipg_clk", + "can0_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_0>; + }; }; -- 2.36.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Marcel Ziswiler <marcel@ziswiler.com> To: devicetree@vger.kernel.org Cc: Liu Ying <victor.liu@nxp.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, linux-imx@nxp.com, Joakim Zhang <qiangqing.zhang@nxp.com>, Marcel Ziswiler <marcel.ziswiler@toradex.com>, Alexander Stein <alexander.stein@ew.tq-group.com>, Fabio Estevam <festevam@gmail.com>, Frank Li <Frank.Li@nxp.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Max Krummenacher <max.krummenacher@toradex.com>, Peng Fan <peng.fan@nxp.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, Philippe Schenker <philippe.schenker@toradex.com>, Rob Herring <robh+dt@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Shawn Guo <shawnguo@kernel.org> Subject: [PATCH v6 05/10] arm64: dts: imx8qxp: add flexcan in adma Date: Thu, 2 Feb 2023 16:32:15 +0100 [thread overview] Message-ID: <20230202153221.197308-6-marcel@ziswiler.com> (raw) In-Reply-To: <20230202153221.197308-1-marcel@ziswiler.com> From: Joakim Zhang <qiangqing.zhang@nxp.com> Add FlexCAN decive in adma subsystem. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # TQMa8XQP --- Changes in v6: - Add Alexander's tested-by. Thanks! Changes in v4: - New patch combining the following downstream patches: commit e8fe3f57223a ("arm64: dts: imx8qxp: add FlexCAN in adma") commit 4e90361f1ed3 ("arm64: dts: imx8qxp: add multi-pd support for CAN1/2") commit 899f516e61f8 ("arm64: dts: imx8: dma: fully switched to new clk binding") commit 8a28ca15a058 ("arm64: dts: imx8qxp: drop multi-pd for CAN device") commit c493402197dd ("arm64: dts: imx8: update CAN fsl,clk-source and fsl,scu-index property") .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 6ccf926b77a5..2dce8f2ee3ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -298,6 +298,65 @@ adc1: adc@5a890000 { status = "disabled"; }; + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8d0000 0x10000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_0>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8e0000 0x10000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_1>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <1>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8f0000 0x10000>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_2>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <2>; + status = "disabled"; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; @@ -369,4 +428,17 @@ adc1_lpcg: clock-controller@5ac90000 { "adc1_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_ADC_1>; }; + + can0_lpcg: clock-controller@5acd0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acd0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; + clock-output-names = "can0_lpcg_pe_clk", + "can0_lpcg_ipg_clk", + "can0_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_0>; + }; }; -- 2.36.1
next prev parent reply other threads:[~2023-02-02 15:37 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-02 15:32 [PATCH v6 00/10] arm64: dts: freescale: prepare and add apalis imx8 support Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-02 15:32 ` [PATCH v6 01/10] arm64: dts: freescale: imx8-ss-lsio: add support for lsio_pwm0-3 Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-02 15:32 ` [PATCH v6 02/10] arm64: dts: imx8-ss-dma: add io-channel-cells to adc nodes Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-02 15:32 ` [PATCH v6 03/10] arm64: dts: freescale: imx8-ss-dma: set lpspi0 max frequency to 60mhz Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-02 15:32 ` [PATCH v6 04/10] firmware: imx: scu-pd: add missed lvds lpi2c and pwm power domains Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler [this message] 2023-02-02 15:32 ` [PATCH v6 05/10] arm64: dts: imx8qxp: add flexcan in adma Marcel Ziswiler 2023-02-02 15:32 ` [PATCH v6 06/10] arm64: dts: imx8qm: add can node in devicetree Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-02 15:32 ` [PATCH v6 07/10] arm64: dts: imx8qm: add vpu decoder and encoder Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-02 15:32 ` [PATCH v6 08/10] dt-bindings: arm: fsl: add toradex,apalis-imx8 et al Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-02 15:32 ` [PATCH v6 09/10] arm64: dts: freescale: add initial apalis imx8 aka quadmax module support Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-02 15:32 ` [PATCH v6 10/10] arm64: dts: freescale: add apalis imx8 aka quadmax carrier board support Marcel Ziswiler 2023-02-02 15:32 ` Marcel Ziswiler 2023-02-03 13:16 ` [PATCH v6 00/10] arm64: dts: freescale: prepare and add apalis imx8 support Marcel Ziswiler 2023-02-03 13:16 ` Marcel Ziswiler
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