From: Alexandre Mergnat <amergnat@baylibre.com> To: Yong Wu <yong.wu@mediatek.com>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat <amergnat@baylibre.com> Subject: [PATCH v3 4/7] arm64: dts: mediatek: add power domain support for mt8365 SoC Date: Fri, 07 Apr 2023 11:34:15 +0200 [thread overview] Message-ID: <20230207-iommu-support-v3-4-97e19ad4e85d@baylibre.com> (raw) In-Reply-To: <20230207-iommu-support-v3-0-97e19ad4e85d@baylibre.com> The following power domain are added to the SoC dts: - MM (MultiMedia) - CONN (Connectivity) - MFG (MFlexGraphics) - Audio - Cam (Camera) - DSP (Digital Signal Processor) - Vdec (Video decoder) - Venc (Video encoder) - APU (AI Processor Unit) Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 110 +++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 386ab8902b55..0e4fa69a2415 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> +#include <dt-bindings/power/mediatek,mt8365-power.h> / { compatible = "mediatek,mt8365"; @@ -282,6 +283,115 @@ syscfg_pctl: syscfg-pctl@10005000 { reg = <0 0x10005000 0 0x1000>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8365-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8365_POWER_DOMAIN_MM { + reg = <MT8365_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "mm", "mm-0", "mm-1", + "mm-2", "mm-3"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + mediatek,infracfg-nao = <&infracfg_nao>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@MT8365_POWER_DOMAIN_CAM { + reg = <MT8365_POWER_DOMAIN_CAM>; + clocks = <&camsys CLK_CAM_LARB2>, + <&camsys CLK_CAM_SENIF>, + <&camsys CLK_CAMSV0>, + <&camsys CLK_CAMSV1>, + <&camsys CLK_CAM_FDVT>, + <&camsys CLK_CAM_WPE>; + clock-names = "cam-0", "cam-1", + "cam-2", "cam-3", + "cam-4", "cam-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_VDEC { + reg = <MT8365_POWER_DOMAIN_VDEC>; + #power-domain-cells = <0>; + }; + + power-domain@MT8365_POWER_DOMAIN_VENC { + reg = <MT8365_POWER_DOMAIN_VENC>; + #power-domain-cells = <0>; + }; + + power-domain@MT8365_POWER_DOMAIN_APU { + reg = <MT8365_POWER_DOMAIN_APU>; + clocks = <&infracfg CLK_IFR_APU_AXI>, + <&apu CLK_APU_IPU_CK>, + <&apu CLK_APU_AXI>, + <&apu CLK_APU_JTAG>, + <&apu CLK_APU_IF_CK>, + <&apu CLK_APU_EDMA>, + <&apu CLK_APU_AHB>; + clock-names = "apu", "apu-0", + "apu-1", "apu-2", + "apu-3", "apu-4", + "apu-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + + power-domain@MT8365_POWER_DOMAIN_CONN { + reg = <MT8365_POWER_DOMAIN_CONN>; + clocks = <&topckgen CLK_TOP_CONN_32K>, + <&topckgen CLK_TOP_CONN_26M>; + clock-names = "conn", "conn1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_MFG { + reg = <MT8365_POWER_DOMAIN_MFG>; + clocks = <&topckgen CLK_TOP_MFG_SEL>; + clock-names = "mfg"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_AUDIO { + reg = <MT8365_POWER_DOMAIN_AUDIO>; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_IFR_AUDIO>, + <&infracfg CLK_IFR_AUD_26M_BK>; + clock-names = "audio", "audio1", "audio2"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_DSP { + reg = <MT8365_POWER_DOMAIN_DSP>; + clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_DSP_26M>; + clock-names = "dsp", "dsp1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Mergnat <amergnat@baylibre.com> To: Yong Wu <yong.wu@mediatek.com>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, Rob Herring <robh+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat <amergnat@baylibre.com> Subject: [PATCH v3 4/7] arm64: dts: mediatek: add power domain support for mt8365 SoC Date: Fri, 07 Apr 2023 11:34:15 +0200 [thread overview] Message-ID: <20230207-iommu-support-v3-4-97e19ad4e85d@baylibre.com> (raw) In-Reply-To: <20230207-iommu-support-v3-0-97e19ad4e85d@baylibre.com> The following power domain are added to the SoC dts: - MM (MultiMedia) - CONN (Connectivity) - MFG (MFlexGraphics) - Audio - Cam (Camera) - DSP (Digital Signal Processor) - Vdec (Video decoder) - Venc (Video encoder) - APU (AI Processor Unit) Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 110 +++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 386ab8902b55..0e4fa69a2415 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> +#include <dt-bindings/power/mediatek,mt8365-power.h> / { compatible = "mediatek,mt8365"; @@ -282,6 +283,115 @@ syscfg_pctl: syscfg-pctl@10005000 { reg = <0 0x10005000 0 0x1000>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8365-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8365_POWER_DOMAIN_MM { + reg = <MT8365_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names = "mm", "mm-0", "mm-1", + "mm-2", "mm-3"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + mediatek,infracfg-nao = <&infracfg_nao>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@MT8365_POWER_DOMAIN_CAM { + reg = <MT8365_POWER_DOMAIN_CAM>; + clocks = <&camsys CLK_CAM_LARB2>, + <&camsys CLK_CAM_SENIF>, + <&camsys CLK_CAMSV0>, + <&camsys CLK_CAMSV1>, + <&camsys CLK_CAM_FDVT>, + <&camsys CLK_CAM_WPE>; + clock-names = "cam-0", "cam-1", + "cam-2", "cam-3", + "cam-4", "cam-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_VDEC { + reg = <MT8365_POWER_DOMAIN_VDEC>; + #power-domain-cells = <0>; + }; + + power-domain@MT8365_POWER_DOMAIN_VENC { + reg = <MT8365_POWER_DOMAIN_VENC>; + #power-domain-cells = <0>; + }; + + power-domain@MT8365_POWER_DOMAIN_APU { + reg = <MT8365_POWER_DOMAIN_APU>; + clocks = <&infracfg CLK_IFR_APU_AXI>, + <&apu CLK_APU_IPU_CK>, + <&apu CLK_APU_AXI>, + <&apu CLK_APU_JTAG>, + <&apu CLK_APU_IF_CK>, + <&apu CLK_APU_EDMA>, + <&apu CLK_APU_AHB>; + clock-names = "apu", "apu-0", + "apu-1", "apu-2", + "apu-3", "apu-4", + "apu-5"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + + power-domain@MT8365_POWER_DOMAIN_CONN { + reg = <MT8365_POWER_DOMAIN_CONN>; + clocks = <&topckgen CLK_TOP_CONN_32K>, + <&topckgen CLK_TOP_CONN_26M>; + clock-names = "conn", "conn1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_MFG { + reg = <MT8365_POWER_DOMAIN_MFG>; + clocks = <&topckgen CLK_TOP_MFG_SEL>; + clock-names = "mfg"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_AUDIO { + reg = <MT8365_POWER_DOMAIN_AUDIO>; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_IFR_AUDIO>, + <&infracfg CLK_IFR_AUD_26M_BK>; + clock-names = "audio", "audio1", "audio2"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_DSP { + reg = <MT8365_POWER_DOMAIN_DSP>; + clocks = <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_DSP_26M>; + clock-names = "dsp", "dsp1"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-04-07 9:35 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-07 9:34 [PATCH v3 0/7] Add IOMMU support to MT8365 SoC Alexandre Mergnat 2023-04-07 9:34 ` Alexandre Mergnat 2023-04-07 9:34 ` [PATCH v3 1/7] arm64: dts: mediatek: add mmsys support for mt8365 SoC Alexandre Mergnat 2023-04-07 9:34 ` Alexandre Mergnat 2023-04-11 8:26 ` AngeloGioacchino Del Regno 2023-04-11 8:26 ` AngeloGioacchino Del Regno 2023-04-07 9:34 ` [PATCH v3 2/7] arm64: dts: mediatek: add camsys " Alexandre Mergnat 2023-04-07 9:34 ` Alexandre Mergnat 2023-04-11 8:26 ` AngeloGioacchino Del Regno 2023-04-11 8:26 ` AngeloGioacchino Del Regno 2023-04-07 9:34 ` [PATCH v3 3/7] arm64: dts: mediatek: add apu " Alexandre Mergnat 2023-04-07 9:34 ` Alexandre Mergnat 2023-04-11 8:26 ` AngeloGioacchino Del Regno 2023-04-11 8:26 ` AngeloGioacchino Del Regno 2023-04-07 9:34 ` Alexandre Mergnat [this message] 2023-04-07 9:34 ` [PATCH v3 4/7] arm64: dts: mediatek: add power domain " Alexandre Mergnat 2023-04-11 8:26 ` AngeloGioacchino Del Regno 2023-04-11 8:26 ` AngeloGioacchino Del Regno 2023-04-07 9:34 ` [PATCH v3 5/7] arm64: dts: mediatek: add smi " Alexandre Mergnat 2023-04-07 9:34 ` Alexandre Mergnat 2023-04-07 9:34 ` [PATCH v3 6/7] arm64: dts: mediatek: add larb " Alexandre Mergnat 2023-04-07 9:34 ` Alexandre Mergnat 2023-04-07 9:34 ` [PATCH v3 7/7] arm64: dts: mediatek: add iommu " Alexandre Mergnat 2023-04-07 9:34 ` Alexandre Mergnat
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