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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Philipp Tomsich <philipp.tomsich@vrull.eu>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw
Date: Tue,  7 Feb 2023 17:09:12 +1000	[thread overview]
Message-ID: <20230207070943.2558857-2-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20230207070943.2558857-1-alistair.francis@opensource.wdc.com>

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The decoding of the following instructions from Zb[abcs] currently
contains decoding/printing errors:
 * xnor,orn,andn: the rs2 operand is not being printed
 * slli.uw: decodes and prints the immediate shift-amount as a
            register (e.g. 'shift-by-2' becomes 'sp') instead of
	    interpreting this as an immediate

This commit updates the instruction descriptions to use the
appropriate decoding/printing formats.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120151551.1022761-1-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index d216b9c39b..ddda687c13 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1626,9 +1626,9 @@ const rv_opcode_data opcode_data[] = {
     { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
@@ -1647,7 +1647,7 @@ const rv_opcode_data opcode_data[] = {
     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
     { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
-- 
2.39.1



  reply	other threads:[~2023-02-07  7:12 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-07  7:09 [PULL 00/32] riscv-to-apply queue Alistair Francis
2023-02-07  7:09 ` Alistair Francis [this message]
2023-02-07  7:09 ` [PULL 02/32] include/hw/riscv/opentitan: update opentitan IRQs Alistair Francis
2023-02-07  7:09 ` [PULL 03/32] hw/riscv: boot: Don't use CSRs if they are disabled Alistair Francis
2023-02-07  7:09 ` [PULL 04/32] target/riscv: Update VS timer whenever htimedelta changes Alistair Francis
2023-02-07  7:09 ` [PULL 05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP Alistair Francis
2023-02-07  7:09 ` [PULL 06/32] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX Alistair Francis
2023-02-07  7:09 ` [PULL 07/32] target/riscv: Ensure opcode is saved for all relevant instructions Alistair Francis
2023-02-07  7:09 ` [PULL 08/32] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Alistair Francis
2023-02-07  7:09 ` [PULL 09/32] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Alistair Francis
2023-02-07  7:09 ` [PULL 10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Alistair Francis
2023-02-07  7:09 ` [PULL 11/32] target/riscv: set tval for triggered watchpoints Alistair Francis
2023-02-07  7:09 ` [PULL 12/32] hw/riscv/boot.c: calculate fdt size after fdt_pack() Alistair Francis
2023-02-07  7:09 ` [PULL 13/32] hw/riscv: split fdt address calculation from fdt load Alistair Francis
2023-02-07  7:09 ` [PULL 14/32] hw/riscv: change riscv_compute_fdt_addr() semantics Alistair Francis
2023-02-07  7:09 ` [PULL 15/32] RISC-V: Adding XTheadCmo ISA extension Alistair Francis
2023-02-07  7:09 ` [PULL 16/32] RISC-V: Adding XTheadSync " Alistair Francis
2023-02-07  7:09 ` [PULL 17/32] RISC-V: Adding XTheadBa " Alistair Francis
2023-02-07  7:09 ` [PULL 18/32] RISC-V: Adding XTheadBb " Alistair Francis
2023-02-07  7:09 ` [PULL 19/32] RISC-V: Adding XTheadBs " Alistair Francis
2023-02-07  7:09 ` [PULL 20/32] RISC-V: Adding XTheadCondMov " Alistair Francis
2023-02-07  7:09 ` [PULL 21/32] RISC-V: Adding T-Head multiply-accumulate instructions Alistair Francis
2023-02-07  7:09 ` [PULL 22/32] RISC-V: Adding T-Head MemPair extension Alistair Francis
2023-02-07  7:09 ` [PULL 23/32] RISC-V: Adding T-Head MemIdx extension Alistair Francis
2023-02-07  7:09 ` [PULL 24/32] RISC-V: Adding T-Head FMemIdx extension Alistair Francis
2023-02-07  7:09 ` [PULL 25/32] RISC-V: Set minimum priv version for Zfh to 1.11 Alistair Francis
2023-02-07  7:09 ` [PULL 26/32] RISC-V: Add initial support for T-Head C906 Alistair Francis
2023-02-07  7:09 ` [PULL 27/32] RISC-V: Adding XTheadFmv ISA extension Alistair Francis
2023-02-07  7:09 ` [PULL 28/32] target/riscv: add a MAINTAINERS entry for XThead* extension support Alistair Francis
2023-02-07  7:09 ` [PULL 29/32] target/riscv: fix for virtual instr exception Alistair Francis
2023-02-07  7:09 ` [PULL 30/32] target/riscv: fix ctzw behavior Alistair Francis
2023-02-07  7:09 ` [PULL 31/32] target/riscv: fix SBI getchar handler for KVM Alistair Francis
2023-02-07  7:09 ` [PULL 32/32] hw/riscv: virt: Simplify virt_{get,set}_aclint() Alistair Francis
2023-02-07 20:12 ` [PULL 00/32] riscv-to-apply queue Peter Maydell

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